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advance data sheet november 1999 orca ? ort4622 field-programmable system chip (fpsc) four-channel x 622 mbits/s backplane transceiver introduction lucent technolo g ies microelectronics group has developed a solution for desi g ners who need the man y advanta g es of fpga-based desi g n implemen- tation, coupled with hi g h-speed serial backplane data transfer. the 622 mbits/s backplane transceiver offers a clockless, hi g h-speed interface for interde- vice communication on a board or across a back- plane. the built-in clock recover y of the ort4622 allows for hi g her s y stem performance, easier-to- desi g n clock domains in a multiboard s y stem, and fewer si g nals on the backplane. network desi g ners will benefit from the backplane transceiver as a net- work termination device. the backplane transceiver offers sonet scramblin g /descramblin g of data and streamlined sonet framin g , pointer movin g and transport overhead handlin g , plus the pro g rammable lo g ic to terminate the network into proprietar y s y s- tems. embedded core features n implemented in an orca series 3 fpga arra y . n allows wide ran g e of applications for sonet net- work termination application as well as g eneric data movin g for hi g h-speed backplane data trans- fer. n hi g h-speed interface (hsi) function for clock/data recover y serial backplane data transfer without external clocks. n hsi function uses lucent technolo g ies microelec- tronics groups proven 622 mbits/s serial interface core. n four-channel hsi function provides 622 mbits/s serial interface per channel for a total chip band- width of 2.5 gbits/s (full duplex). n lvds i/os for hsi compliant with eia *-644. n 8:1 data multiplexin g /demultiplexin g for 77.76 mhz b y te-wide data processin g in fpga lo g ic. n on-chip phase-lock loop (pll) clock meets b jitter tolerance specification of itu-t recommendation g.958. n powerdown option of hsi receiver on a per- channel basis. n pseudo-sonet protocol includin g a1/a2 framin g . n sonet scramblin g and descramblin g for required ones densit y (optional). n selected transport overhead (toh) b y tes insertion and extraction for interdevice communication via the toh serial link. n streamlined pointer processor (pointer mover) for 8 khz frame ali g nment. n fifos ali g n incomin g data across all four channels for sts-48 operation (in quad sts-12 format). n independent data stream enables in pseudo- sonet processor. n supports sts-12/sts-48 redundanc y b y either software or hardware control for protection switch- in g applications. * eia is a registered trademark of electronic industries associa- tion. table 1. orca ort4622available fpga logic ? the embedded core and interface are not included in the above gate counts. the usable gate count range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates per pfu/slic), including 12 gates pre-lut/ff pair (eight per pfu), and 12 gates per slc/ff pair (one per pfu). each o f the four pios per pic is counted as 16 gates (two ffs, fast-capture latch, output logic, clk drivers, and i/o buffers). pfus used a s ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. device usable gates ? number of luts number of registers max user ram max user i/os array size number of pfus ort4622 60k120k 4032 5304 64k 259 18 x 28 504
table of contents contents page contents page orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies 2 introduction.................................................................1 embedded core features ..........................................1 fpsc highlights .........................................................4 software support........................................................4 description..................................................................5 what is an fpsc? ...................................................5 fpsc overview .......................................................5 fpsc gate counting ...............................................5 fpga/embedded core interface .............................5 orca foundry development system .....................5 fpsc design kit ......................................................6 fpga logic overview..............................................6 plc logic ................................................................6 pic logic .................................................................7 system features ......................................................7 routing.....................................................................7 configuration............................................................7 more series 3 information........................................7 ort4622 overview ....................................................8 device layout ..........................................................8 backplane transceiver interface .............................8 hsi interface ..........................................................10 stm macrocell ....................................................... 10 cpu interface ........................................................ 10 fpga interface ...................................................... 10 fpsc configuration ............................................... 10 backplane transceiver core detailed description ... 12 hsi macro .............................................................. 12 stm transmitter (fpga -> backplane) ................. 14 stm receiver (backplane -> fpga) ..................... 15 powerdown mode .................................................. 21 redundancy and protection switching .................. 21 memory map.............................................................22 definition of register types ...................................22 memory map overview ..........................................23 memory map bit descriptions ................................27 absolute maximum ratings......................................32 recommend operating conditions ..........................32 electrical characteristics ..........................................33 hsi circuit specifications .........................................35 input data ..............................................................35 jitter tolerance ......................................................35 generated output jitter .........................................35 pll.........................................................................35 input reference clock............................................35 lvds i/o ..................................................................36 lvds receiver buffer requirements.....................37 timing characteristics ..............................................38 input/output buffer measurement conditions ..........46 fpga output buffer characteristics.........................47 estimating power dissipation ...................................48 pin information .........................................................49 package thermal characteristics summary ............73 q ja .........................................................................73 y jc .........................................................................73 q jc ........................................................................73 q jb ........................................................................73 fpga maximum junction temperature.................73 package thermal characteristics.............................74 package coplanarity ................................................74 package parasitics ...................................................74 package outline diagrams.......................................76 terms and definitions ............................................76 432-pin ebga........................................................77 680-pin pbgam.....................................................78 ordering information.................................................79
lucent technologies inc. 3 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver table of contents (continued) figure page table page figure 1. orca ort4622 block diagram................. 8 figure 2. ort4622 array ........................................... 9 figure 3. architecture of ort4622 backplane transceiver .......................................... 11 figure 4. hsi functional block diagram .................. 13 figure 5. byte ordering of input/output interface in sts-12 mode ........................................................ 14 figure 6. framer circuit ........................................... 16 figure 7. interconnect of streams for fifo alignment ..................................................... 17 figure 8. alignment of four sts-12 streams .......... 17 figure 9. examples of link alignment...................... 18 figure 10. pointer mover state machine.................. 20 figure 11. transmit parallel port timing (backplane -> fpga) ............................................ 38 figure 12. transmit transport delay (fpga -> backplane) ........................................... 39 figure 13. receive parallel port timing (backplane -> fpga) ............................................ 40 figure 14. protection switch timing......................... 41 figure 15. toh input serial port timing (fpga -> backplane) ............................................ 42 figure 16. toh output serial port timing (backplane -> fpga) ............................................ 43 figure 17. cpu write transaction ........................... 44 figure 18. cpu read transaction ........................... 45 figure 19. ac test loads .......................................... 46 figure 20. output buffer delays............................... 46 figure 21. input buffer delays.................................. 46 figure 22. sinklim (t j = 25 c, v dd = 3.3 v)............ 47 figure 23. slewlim (t j = 25 c, v dd = 3.3 v) ........... 47 figure 24. fast (t j = 25 c, v dd = 3.3 v) ................ 47 figure 25. sinklim (t j = 125 c, v dd = 3.0 v).......... 47 figure 26. slewlim (t j = 125 c, v dd = 3.0 v) ......... 47 figure 27. fast (t j = 125 c, v dd = 3.0 v) .............. 47 figure 28. package parasitics ................................. 75 table page table 1. orca ort4622available fpga logic ... 1 table 2. valid starting positions for an sts-mc ..... 19 table 3. spe and c1j1 functionality ...................... 21 table 4. structural register elements ..................... 22 table 5. memory map.............................................. 23 table 6. memory map bit descriptions.................... 27 table 7. absolute maximum ratings ....................... 32 table 8. recommend operating conditions............ 32 table 9. electrical characteristics for fpga i/o...... 33 table 10. electrical characteristics for embedded core i/o other than lvds i/o............................... 34 table 11. jitter tolerance......................................... 35 table 12. pll .......................................................... 35 table 13. input reference clock ............................. 35 table 14. lvds driver dc data................................ 36 table 15. lvds driver ac data................................ 36 table 16. lvds receiver dc data ........................... 37 table 17. lvds receiver ac data ........................... 37 table 18. lvds receiver power consumption ....... 37 table 19. lvds operating parameters ................... 37 table 20. timing requirements (transmit parallel port timing).............................. 38 table 21. timing requirements (transmit transport delay).................................... 39 table 22. timing requirements (receive parallel port timing)............................... 40 table 23. timing requirements (protection switch timing) .................................... 41 table 24. timing requirements (toh input serial port timing) .............................. 42 table 25. timing requirements (toh output serial port timing) ........................... 43 table 26. timing requirements (cpu write transaction) ....................................... 44 table 27. timing requirements (cpu read transaction) ....................................... 45 table 28. fpga common-function pin description ..................................................... 49 table 29. fpsc function pin description ............... 52 table 30. embedded core/fpga interface signal description .................................. 54 table 31. embedded core/fpga interface signal locations ..................................... 56 table 32. 432-pin ebga pinout .............................. 58 table 33. 680-pin pbgam pinout ........................... 64 table 34. orca ort4622 plastic package thermal guidelines ................................ 74 table 35. orca ort4622 package parasitics ...... 75 table 36. voltage options ....................................... 79 table 37. temperature options ............................... 79 table 38. package type options............................. 79 table 39. orca series 3+ package matrix ............ 79
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 4 lucent technologies inc. lucent technologies inc. fpsc highlights n implemented as an embedded core in the orca series 3+ fpsc architecture. n allows the user to integrate the core with up to 120k gates of programmable logic (all in one device) and provides up to 242 user i/os in addition to the embedded core i/o pins. n fpga portion retains all of the features of the orca series 3 fpga architecture: high-performance, cost-effective, 0.25 m, 5-level metal technology. twin-quad programmable function unit (pfu) architecture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu. supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each programmable logic cell (plc). up to three expressclk inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. dual-use microprocessor interface (mpi) can be used for configuration, as well as for a general- purpose interface to the fpga. glueless interface to i960 ? and powerpc ? processors with user- configurable address space provided. programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be com- bined with fpga logic to create complex functions, such as digital phase-locked loops, frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. true internal 3-state, bidirectional buses with simple control provided by the slic. 32 x 4 ram per pfu, configurable as single or dual port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. built-in boundary scan ( ieee 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. n high-speed on-chip interface provided between fpga logic and embedded core to reduce bottle- necks typically found when interfacing off-chip. software support n supported by orca foundry software and third- party cae tools for implementing orca series 3+ devices and simulation/timing analysis with the embedded core functions. n embedded core configuration options and simulation netlists generated by fpsc configuration manager utility. * pal is a trademark of advanced micro devices, inc. ? i960 is a registered trademark of intel corporation. ? powerpc is a registered trademark of international business machines corporation. ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
lucent technologies inc. 5 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. description what is an fpsc? fpscs, or field-programmable system chips, are devices that combine field-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and flexibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lucents series 3+ fpscs are created from series 3 orca fpgas. to create a series 3+ fpsc, several rows of programmable logic cells (see fpga logic overview section for fpga logic details) are removed from a series 3 orca fpga, and the area is replaced with an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 efficiency, none of the fpga functionality is changedall of the series 3 fpga capability is retained: mpi, pcms, boundary scan, etc. the rows of programmable logic are replaced at the bottom of the device, allowing pins on the bottom and sides of the replaced rows to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga functionality as do special function fpga pins within the embedded core area. the embedded cores can take many forms and gener- ally come from lucent technologies asic libraries. future offerings will allow customers to supply their own core functions for the creation of custom fpscs. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell/asic gates are, however, 10 to 25 times more silicon area efficient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core is designed to look like fpga i/os from the fpga side, simplifying interface signal routing and pro- viding a unified approach with general fpga design. effectively, the fpga is designed as if signals were going off of the device to the embedded core, but the on-chip interface is much faster than going off-chip and requires less power. all of the delays for the interface are precharacterized and accounted for in the orca foundry development system. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clocking between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system flexibility, fpga configuration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality sim- ply by reconfiguring the device. orca foundry development system the orca foundry development system is used to process a design from a netlist to a configured fpsc. this system is used to map a design onto the orca architecture and then place and route it using orca foundrys timing-driven tools. the development system also includes interfaces to, and libraries for, other popu- lar cae tools for design entry, synthesis, simulation, and timing analysis. the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured fpsc. in the design flow, the user defines the functionality of the fpga portion of the fpsc and embedded core settings at two points in the design flow: at design entry and at the bit stream generation stage. following design entry, the develop- ment systems map, place, and route tools translate the netlist into a routed fpsc. a static timing analysis tool is provided to determine device speed and a back- annotated netlist can be created to allow simulation.
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 6 lucent technologies inc. lucent technologies inc. description (continued) timing and simulation output files from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the configuration data which is loaded into the fpscs internal configuration ram. when using the bit stream generator, the user selects options that affect the functionality of the fpsc. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. fpsc design kit development is facilitated by an fpsc design kit which, together with orca foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc configuration manager, hdl gate-level structural netlists, all necessary synthesis libraries, and complete online documentation. the kit's software couples with orca foundry, providing a seamless fpsc design environment. more information can be obtained by vis- iting the orca website or contacting a local sales office, both listed on the last page of this document. fpga logic overview orca series 3 fpga logic is a new generation of sram-based fpga logic built on the successful series 2 fpga line from lucent technologies micro- electronics group, with enhancements and innovations geared toward todays high-speed designs on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca series 2 devices, the series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 3 devices con- tain many new patented enhancements and are offered in a variety of packages, speed grades, and tempera- ture ranges. orca series 3 fpga logic consists of three basic ele- ments: programmable logic cells (plcs), programma- ble input/output cells (pics), and system-level features. an array of plcs is surrounded by pics. each plc contains a programmable function unit (pfu), a sup- plemental logic and interconnect cell (slic), local rout- ing resources, and configuration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be per- formed in the slic. the pics provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. some of the sys- tem-level functions include the new microprocessor interface ( mpi ) and the programmable clock manager ( pcm ). plc logic each pfu within a plc contains eight 4-input (16-bit) look-up tables (luts), eight latches/flip-flops (ffs), and one additional flip-flop that may be used indepen- dently or with arithmetic functions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert (aoi) to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu out- puts make fast, true 3-state buses possible within the fpga logic, reducing required routing and allowing for real-world system performance.
lucent technologies inc. 7 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. description (continued) pic logic the series 3 pic addresses the demand for ever- increasing system clock speeds. each pic contains four programmable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk . this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca series 2 capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o buffer associated with each pad is the same as the orca series 3 buffer. system features the series 3 also provides system-level functionality by means of its dual-use microprocessor interface (mpi) and its innovative programmable clock manager (pcm). these functional blocks allow for easy glueless system interfacing and the capability to adjust to vary- ing conditions in todays high-speed systems. since these and all other series 3 features are available in every series 3+ fpsc, they can also interface to the embedded core providing for easier system integration. routing the abundant routing resources of orca series 3 fpga logic are organized to route signals individually or as buses with related control signals. clocks are routed on a low-skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. expressclks may be glitchlessly and independently enabled and disabled with a programmable control sig- nal using the stopclk feature. the improved pic rout- ing resources are now similar to the patented intra-plc routing resources and provide great flexibility in moving signals to and from the pios. this flexibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to specific pins. configuration the fpga logics functionality is determined by inter- nal configuration ram. the fpga logics internal ini- tialization/configuration circuitry loads the configuration data at powerup or under system control. the ram is loaded by using one of several configuration modes, including serial eeprom, the microprocessor inter- face, or the embedded function core. more series 3 information for more information on series 3 fpgas, please refer to the series 3 fpga data sheet, available on the orca worldwide website or by contacting lucent technologies as directed on the back of this data sheet.
8 8 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. ort4622 overview device layout the ort4622 fpsc provides a high-speed backplane transceiver combined with fpga logic. the device is based on a 2.5 v/3.3 v or3l125b fpga. the or3l125b has a 28 x 28 array of programmable logic cells (plcs). for the ort4622, the bottom ten rows of plcs in the array were replaced with the embedded backplane transceiver core. the ort4622 embedded core comprises the hsi macrocell, the synchronous transport module (stm) macrocell, a cpu interface, and lvds i/os. the four full-duplex channels perform data transfer, scrambling/descrambling and framing at the rate of 622 mbits/s. figure 1 shows the ort4622 block diagram. figure 2 shows a schematic view of the ort4622. the upper portion of the device is an 18 x 28 array of plcs surrounded on the left, top, and right by programmable input/output cells (pics). at the bottom of the plc array are the core interface cells (cics) connecting to the embedded core region. the embedded core region contains the backplane transceiver functionality of the device. it is surrounded on the left, bottom, and right by backplane transceiver dedicated i/os as well as power and special function fpga pins. also shown are the interquad routing blocks (hiq, viq) present in the series 3 fpga devices. system-level functions (located in the corners of the plc array), routing resources, and configuration ram are not shown in figure 2 . backplane transceiver interface the advantage of the ort4622 fpsc is to bring spe- cific networking functions to an early market presence with programmable logic in fpga system. the 622 mbits/s backplane transceiver core allows the ort4622 to communicate across a backplane or on a given board at an aggregate speed of 2.5 gbits/s, pro- viding a physical medium for high-speed asynchronous serial data transfer between system devices. this device is intended for, but not limited to, connecting ter- minal equipment in sonet/sdh and atm systems. for networking applications, the ort4622 offers a sonet framer and scrambler/descrambler interface capable of frame synchronization and insertion/extrac- tion of selectable transport overhead bytes and sonet scrambling and descrambling for four sts-12 (622 mbits/s) channels. the channels are synchro- nized to each other by a user provided 8 khz frame pulse. the ort4622 also provides sts-48 (2.5 gbits/s) operation across all four channels as long as each channel is in sts-12 format. figure 3 shows the architecture of the ort4622 backplane transceiver core. 5-8113(f) figure 1. orca ort4622 block diagram ? clock/data recovery 4 full- duplex serial channels byte- wide data fpga logic standard fpga i/os lv d s 622 mbits/s data 622 mbits/s data stm ? pointer mover ? scrambling ? fifo alignment ? toh processor i/os hsi
lucent technologies inc. 9 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. ort4622 overview (continued) figure 2. ort4622 array iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt10 pt11 pt12 pt13 pt14 pt15 pt16 pt17 pt18 pt19 pt20 pt21 pt22 pt23 pt24 pt25 pt26 pt27 pt28 iiii pl1 r1 c1 r1 c2 r1 c3 r1 c4 r1 c5 r1 c6 r1 c7 r1 c8 r1 c9 r1 c10 r1 c11 r1 c12 r1 c13 r1 c14 r1 c15 r1 c16 r1 c17 r1 c18 r1 c19 r1 c20 r1 c21 r1 c22 r1 c23 r1 c24 r1 c25 r1 c26 r1 c27 r1 c28 pr1 iiii iiii pl2 r2 c1 r2 c2 r2 c3 r2 c4 r2 c5 r2 c6 r2 c7 r2 c8 r2 c9 r2 c10 r2 c11 r2 c12 r2 c13 r2 c14 r2 c15 r2 c16 r2 c17 r2 c18 r2 c19 r2 c20 r2 c21 r2 c22 r2 c23 r2 c24 r2 c25 r2 c26 r2 c27 r2 c28 pr2 iiii iiii pl3 r3 c1 r3 c2 r3 c3 r3 c4 r3 c5 r3 c6 r3 c7 r3 c8 r3 c9 r3 c10 r3 c11 r3 c12 r3 c13 r3 c14 r3 c15 r3 c16 r3 c17 r3 c18 r3 c19 r3 c20 r3 c21 r3 c22 r3 c23 r3 c24 r3 c25 r3 c26 r3 c27 r3 c28 pr3 iiii iiii pl4 r4 c1 r4 c2 r4 c3 r4 c4 r4 c5 r4 c6 r4 c7 r4 c8 r4 c9 r4 c10 r4 c11 r4 c12 r4 c13 r4 c14 r4 c15 r4 c16 r4 c17 r4 c18 r4 c19 r4 c20 r4 c21 r4 c22 r4 c23 r4 c24 r4 c25 r4 c26 r4 c27 r4 c28 pr4 iiii iiii pl5 r5 c1 r5 c2 r5 c3 r5 c4 r5 c5 r5 c6 r5 c7 r5 c8 r5 c9 r5 c10 r5 c11 r5 c12 r5 c13 r5 c14 r5 c15 r5 c16 r5 c17 r5 c18 r5 c19 r5 c20 r5 c21 r5 c22 r5 c23 r5 c24 r5 c25 r5 c26 r5 c27 r5 c28 pr5 iiii iiii pl6 r6 c1 r6 c2 r6 c3 r6 c4 r6 c5 r6 c6 r6 c7 r6 c8 r6 c9 r6 c10 r6 c11 r6 c12 r6 c13 r6 c14 r6 c15 r6 c16 r6 c17 r6 c18 r6 c19 r6 c20 r6 c21 r6 c22 r6 c23 r6 c24 r6 c25 r6 c26 r6 c27 r6 c28 pr6 iiii iiii pl7 r7 c1 r7 c2 r7 c3 r7 c4 r7 c5 r7 c6 r7 c7 r7 c8 r7 c9 r7 c10 r7 c11 r7 c12 r7 c13 r7 c14 r7 c15 r7 c16 r7 c17 r7 c18 r7 c19 r7 c20 r7 c21 r7 c22 r7 c23 r7 c24 r7 c25 r7 c26 r7 c27 r7 c28 pr7 iiii iiii pl8 r8 c1 r8 c2 r8 c3 r8 c4 r8 c5 r8 c6 r8 c7 r8 c8 r8 c9 r8 c10 r8 c11 r8 c12 r8 c13 r8 c14 r8 c15 r8 c16 r8 c17 r8 c18 r8 c19 r8 c20 r8 c21 r8 c22 r8 c23 r8 c24 r8 c25 r8 c26 r8 c27 r8 c28 pr8 iiii iiii pl9 r9 c1 r9 c2 r9 c3 r9 c4 r9 c5 r9 c6 r9 c7 r9 c8 r9 c9 r9 c10 r9 c11 r9 c12 r9 c13 r9 c14 r9 c15 r9 c16 r9 c17 r9 c18 r9 c19 r9 c20 r9 c21 r9 c22 r9 c23 r9 c24 r9 c25 r9 c26 r9 c27 r9 c28 pr9 iiii iiii pl10 r10 c1 r10 c2 r10 c3 r10 c4 r10 c5 r10 c6 r10 c7 r10 c8 r10 c9 r10 c10 r10 c11 r10 c12 r10 c13 r10 c14 r10 c15 r10 c16 r10 c17 r10 c18 r10 c19 r10 c20 r10 c21 r10 c22 r10 c23 r10 c24 r10 c25 r10 c26 r10 c27 r10 c28 pr10 iiii iiii pl11 r11 c1 r11 c2 r11 c3 r11 c4 r11 c5 r11 c6 r11 c7 r11 c8 r11 c9 r11 c10 r11 c11 r11 c12 r11 c13 r11 c14 r11 c15 r11 c16 r11 c17 r11 c18 r11 c19 r11 c20 r11 c21 r11 c22 r11 c23 r11 c24 r11 c25 r11 c26 r11 c27 r11 c28 pr11 iiii iiii pl12 r12 c1 r12 c2 r12 c3 r12 c4 r12 c5 r12 c6 r12 c7 r12 c8 r12 c9 r12 c10 r12 c11 r12 c12 r12 c13 r12 c14 r12 c15 r12 c16 r12 c17 r12 c18 r12 c19 r12 c20 r12 c21 r12 c22 r12 c23 r12 c24 r12 c25 r12 c26 r12 c27 r12 c28 pr12 iiii iiii pl13 r13 c1 r13 c2 r13 c3 r13 c4 r13 c5 r13 c6 r13 c7 r13 c8 r13 c9 r13 c10 r13 c11 r13 c12 r13 c13 r13 c14 r13 c15 r13 c16 r13 c17 r13 c18 r13 c19 r13 c20 r13 c21 r13 c22 r13 c23 r13 c24 r13 c25 r13 c26 r13 c27 r13 c28 pr13 iiii iiii pl14 r14 c1 r14 c2 r14 c3 r14 c4 r14 c5 r14 c6 r14 c7 r14 c8 r14 c9 r14 c10 r14 c11 r14 c12 r14 c13 r14 c14 r14 c15 r14 c16 r14 c17 r14 c18 r14 c19 r14 c20 r14 c21 r14 c22 r14 c23 r14 c24 r14 c25 r14 c26 r14 c27 r14 c28 pr14 iiii iiii pl15 r15 c1 r15 c2 r15 c3 r15 c4 r15 c5 r15 c6 r15 c7 r15 c8 r15 c9 r15 c10 r15 c11 r15 c12 r15 c13 r15 c14 r15 c15 r15 c16 r15 c17 r15 c18 r15 c19 r15 c20 r15 c21 r15 c22 r15 c23 r15 c24 r15 c25 r15 c26 r15 c27 r15 c28 pr15 iiii iiii pl16 r16 c1 r16 c2 r16 c3 r16 c4 r16 c5 r16 c6 r16 c7 r16 c8 r16 c9 r16 c10 r16 c11 r16 c12 r16 c13 r16 c14 r16 c15 r16 c16 r16 c17 r16 c18 r16 c19 r16 c20 r16 c21 r16 c22 r16 c23 r16 c24 r16 c25 r16 c26 r16 c27 r16 c28 pr16 iiii iiii pl17 r17 c1 r17 c2 r17 c3 r17 c4 r17 c5 r17 c6 r17 c7 r17 c8 r17 c9 r17 c10 r17 c11 r17 c12 r17 c13 r17 c14 r17 c15 r17 c16 r17 c17 r17 c18 r17 c19 r17 c20 r17 c21 r17 c22 r17 c23 r17 c24 r17 c25 r17 c26 r17 c27 r17 c28 pr17 iiii iiii pl18 r18 c1 r18 c2 r18 c3 r18 c4 r18 c5 r18 c6 r18 c7 r18 c8 r18 c9 r18 c10 r18 c11 r18 c12 r18 c13 r18 c14 r18 c15 r18 c16 r18 c17 r18 c18 r18 c19 r18 c20 r18 c21 r18 c22 r18 c23 r18 c24 r18 c25 r18 c26 r18 c27 r18 c28 pr18 iiii ii asb1 asb2 asb3 asb4 asb5 asb6 asb7 asb8 asb9 asb10 asb11 asb12 asb13 asb14 asb15 asb16 asb17 asb18 asb19 asb20 asb21 asb22 asb23 asb24 asb25 asb26 asb27 a sb28 ii ii embedded core area ii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 10 lucent technologies inc. lucent technologies inc. ort4622 overview (continued) hsi interface the high-speed interconnect (hsi) macrocell is used for clock/data recovery and mux/demux between 77.76 mhz byte-wide internal data buses and 622 mbits/s external serial links. the hsi interface receives four 622 mbits/s serial input data streams from the lvds inputs and provides four independent 77.76 mhz byte-wide data streams and recovered clock to the stm macro. there is no require- ment for bit alignment since sonet type framing will take place inside the ort4622 core. for transmit, the hsi converts four byte-wide 77.76 mhz data streams to serial streams at 622 mbits/s at the lvds outputs. stm macrocell the stm portion of the embedded core consists of transmitter (tx) and receiver (rx) sections. the stm receives four byte-wide data streams at 77.76 mhz and the associated clock from the hsi. the incoming streams are sonet framed and descrambled before they are written into a fifo which absorbs phase and delay variations and allows the shift to the system clock. the toh is then extracted and sent out on the four serial ports. the pointer interpreter will then put the synchronous transport signal (sts) synchronous payload envelopes (spe) into a small elastic store from which the pointer generator will produce four byte-wide sts-12 streams of data that are aligned to the system timing pulse. transmitted data for each channel is received through a parallel bus and a serial port from the fpga circuit. toh bytes are received from the serial input port and can be optionally inserted from programmable registers or serial inputs to the sts-12 frame via the toh processor. each of the four parallel input buses is synchronized to a free-running system clock. then the spe and toh data is transferred to the hsi. the stm macrocell also has a scrambler/descrambler disable feature, allowing the user to disable the scram- bler of the transmitter and the descrambler of the receiver. cpu interface the embedded core has a dedicated, asynchronous, mpc860 compatible, cpu interface that is used for de- vice setup, control, and monitoring. dual sets of i/o pins of this cpu interface with a bit stream configurable scheme provide designers a convenient and flexible op- tion for configuration. one set of cpu i/o pins goes off chip allowing direct connection with an onboard cpu. another set of cpu i/o pins are available to the fpga logic allowing for a stand-alone system free of an exter- nal cpu interface. the cpu interface is composed of an 8-bit data bus, a 7-bit address bus, a chip select signal, a read/write sig- nal, and an interrupt signal. fpga interface the fpga logic will receive/transmit frame aligned streams of 77.76 mhz data (maximum of four streams in each direction) from/to the backplane transceiver embedded core. all frames transmitted to the fpga will be aligned to the fpga frame pulse which will be provided by the fpga users logic to the stm macro. all frames received from the fpga logic will be aligned to the system frame pulse that will be supplied to the stm macro from the fpga users logic. fpsc configuration configuration of the ort4622 occurs in two stages, fpga bit stream configuration and embedded core setup. fpga configuration the fpga logic is configured by standard fpga bit stream configuration means as discussed in the series 3 fpga data sheet. additionally, for the ort4622, the location of the cpu interface to the embedded core, either on the device pins or at the fpga/embedded core boundary, is configured via fpga configuration and is defined via the ort4622 design kit. embedded core setup the embedded core operation is set up via the embed- ded core cpu of the interface. all options for the oper- ation of the core are configured according to the device register map presented in the detailed description sec- tion of this data sheet.
lucent technologies inc. 11 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. ort4622 overview (continued) 5-8576 (f) figure 3. architecture of ort4622 backplane transceiver tx toh processor frame proc. tx ch a (macro) tx toh processor frame proc. tx ch b (macro) tx toh processor frame proc. tx ch d (macro) tx toh processor frame proc. tx ch c (macro) line lbpk (soft ctl) to rx toh proc. quad channel transmitter /8 pll rx ch a (macrocell) 77.76 mhz fifo pointer mover sts48 ch a rx ch b (macrocell) 77.76 mhz ch b rx ch c (macrocell) 77.76 mhz ch c rx ch d (macrocell) 77.76 mhz ch d lvds lpbk (soft ctl) soft ctl soft ctl soft ctl soft ctl soft ctl soft ctl device i/o rx toh processor toh clk quad channel receiver ch a ch b soft ctl ch c ch d soft ctl toh rx b toh rx c toh rx d rx toh frame toh clk tx toh clk ena toh tx a toh tx b input bus a tx bus b toh tx c tx bus c toh tx d tx bus d system frame line frame prot switch a/b data rx bus a data rx bus b prot switch c/d data rx bus c data rx bus c 2 2 2 2 2 2 2 2 lvds out a lvds out b lvds out c lvds out d lvds in a lvds in b lvds in c lvds in d fpga i/f signals cpu interface (async) int_n 8 data 7 addr rd/wr_n cs_n rst_n device i/o or fpga i/f signals (bit stream selectable) soft ctl soft ctl rx toh clk ena 622 mhz clks ref fdbk 77.76 mhz 622 mhz 77.76 mhz frame clock toh rx a toh_en system clock (77.76 mhz) 12 12 12 12
12 12 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. backplane transceiver core detailed description hsi macro the high-speed interface (hsi) provides a physical medium for high-speed asynchronous serial data trans- fer between the ort4622 and other devices. the devices can be mounted on the same board or mounted on different boards and connected through the shelf backplane. the 622 mbits/s cdr macro is a four-channel clock phase select (cps) and data retime function with serial to parallel demultiplexing for the incoming data stream and parallel to serial multiplexing for outgoing data. the hsi macro consists of three functionally independent blocks: receiver, transmitter, and pll synthesizer as shown in figure 4. the pll synthesizer block receives a 77.76 mhz refer- ence clock at its input, and provides a phase-locked 622.08 mhz clock to the transmitter block and phase control signal to the receiver block. the pll synthe- sizer block is a common asset shared by four receive and transmit channels. the hsi receiver receives four channels of differential 622.08 mbits/s serial data without clock at its lvds receive inputs. the received data must be scrambled, conforming to sonet sts-12 and sdh stm-4 data formats using either a pn7 or pn9 sequence. the pn7 characteristic polynomial is 1 + x 6 + x 7 and pn9 char- acteristic polynomial is 1 + x 4 + x 9 . the clock phase select and data retime (cps/dr) module performs a clock recovery and data retiming function by using phase control information. the resultant 622.08 mbits/s data and clock are then passed to the deserializer module, which performs serial to parallel conversion and provides a 77.76 mbits/s parallel data and clock at its output. the hsi transmitter receives four channels of 77.76 mbits/s parallel data that is synchronous to the reference clock at its inputs. the serializer performs a parallel to serial conversion using a 622.08 mhz clock provided by the pll/synthesizer block. the 622 mbits/s serial data streams are then transmitted through the lvds drivers.
lucent technologies inc. 13 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. backplane transceiver core detailed description (continued) 5-8592 (f) figure 4. hsi functional block diagram 622.08 mhz pll synthesizer 50 w 50 w loopbken clock/data alignment phase adjustment demux 622 mbits/s serial to 78 mhz parallel loop- back hsi_rx 622 mbits/s data 622 mhz clock 8 mux 78 mhz parallel to 622 mbits/s serial bs-mux 100 w loop- back hdout 622 mbits/s 622.08 mhz clock hsi_tx 622 mbits/s data (77.76 mhz ref clock) ref78 rext (resistor) 622 mbits/s data lvds buffer 8 (77.76 mbytes data) (77.76 mbits/s data) (77.76 mhz clock) 77.76 mhz 77.76 mbytes data bscanen hdin 622 mbits/s lvds buffer select boundary- scan control
14 14 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. backplane transceiver core detailed description (continued) stm transmitter (fpga -> backplane) the stm has four sts-12 transmit channels which can be treated as a single sts-48 channel. in general, the transmitter circuit receives four byte-wide 77.76 mhz data from the fpga which nominally represents four sts-12 streams (a, b, c, and d). this data is synchro- nized to the system (reference) clock and an 8 khz system frame pulse from the fpga logic. transport overhead bytes are then optionally inserted into these streams and the streams are forwarded to the hsi. all byte timing pulses required to isolate individual over- head bytes (e.g., a1, a2, b1, d1d3, etc.) are gener- ated internally based on the system frame pulse (sys_fp) received from the fpga logic. all streams operate byte-wide at 77.76 mhz in all modes. the toh processor operates from 25 mhz to 77.76 mhz and supports the following toh signals: a1 and a2 inser- tion and optional corruption; h1, h2, and h3 pass transparently; bip-8 parity calculation (after scram- bling) and b1 byte insertion and optional corruption (before scrambling); optional k1 and k2 insert; optional s1/m0 insert; optional e1/f1/e2 insert; optional section and line data communication channel (dcc, d1d3) insertion (for intercard communications channel); scrambling of outgoing data stream with optional scrambler disabling; optional stream disabling. when the ort4622 is used in nonnetworking applica- tions as a generic high-speed backplane data mover, the toh serial ports are unused or can be used for slow-speed off-channel communication between devices. data received on the parallel bus is optionally scrambled and transferred to lvds outputs. byte ordering information the core supports quad sts-12 mode of operation on the input/output ports. sts-48 is also supported when received in quad sts-12 format. when operating in quad sts-12 mode, each of the independent byte streams carries an entire sts-12 within it. figure 5 reveals the byte ordering of the individual sts-12 streams and for sts-48 operation. 5-8574 (f) figure 5. byte ordering of input/output interface in sts-12 mode 12 24 36 48 9 21 33 45 6 18 30 42 3 15 27 39 11 23 35 47 8 20 32 44 5 17 29 41 2 14 26 38 10 22 34 46 7 19 31 43 4 16 28 40 1 13 25 37 1, 12 2, 12 3, 12 4, 12 1, 9 2, 9 3, 9 4, 9 1, 6 2, 6 3, 6 4, 6 1, 3 2, 3 3, 3 4, 3 1, 11 2, 11 3, 11 4, 11 1, 8 2, 8 3, 8 4, 8 1, 5 2, 5 3, 5 4, 5 1, 2 2, 2 3, 2 4, 2 1, 10 2, 10 3, 10 4, 10 1, 7 2, 7 3, 7 4, 7 1, 4 2, 4 3, 4 4, 4 1, 1 2, 1 3, 1 4, 1 sts-12 #1 sts-12 #2 sts-12 #3 sts-12 #4 sts-12 #1 sts-12 #2 sts-12 #3 sts-12 #4 sts-48 in quad sts-12 format quad sts-12
lucent technologies inc. 15 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. backplane transceiver core detailed description (continued) transport overhead insertion (serial link) the toh serial links are used to insert toh bytes into the transmit data. the transmit toh data and toh_clk_en get retimed by toh_clk in order to meet setup and hold specifications of the device. the retimed toh data is shifted into a 288-bit (32-bit by 9-bit) shift register and then multiplexed as an 8-bit bus to be inserted into the byte-wide data stream. insertion or passthrough of toh is under software con- trol. a1/a2 frame insert and testing all 12 a1 bytes of each sts-12 are set to 0xf6 and all 12 a2 bytes of the sts-12 are set to 0x28 when not overridden with a user-specified value for testing. a1/a2 testing (corruption) is controlled per stream by the a1/a2 error insert register. when a1/a2 corruption detection is set for a particular stream, the a1/a2 val- ues in the corrupted a1/a2 value registers are sent for the number of frames defined in the corrupted a1/a2 frame count register. when the corrupted a1/a2 frame count register is set to zero, a1/a2 corruption will con- tinue until the a1/a2 error insert register is cleared. on a per-device basis, the a1 and a2 byte values are set, as well as the number of frames of corruption. then, to insert the specified a1/a2 values, each chan- nel has an enable register. when the enable register is set, the a1/a2 values are corrupted for the number specified in the number of frames to corrupt. to insert errors again, the per-channel fault insert register must be cleared, and set again. only the last a1 and the first a2 are corrupted. b1 calculation and insertion the b1 calculation block computes a bip-8 code, using even parity over all bits of the previous sts-12 frame after scrambling and is inserted in the b1 byte of the current sts-12 frame before scrambling. per-bit b1 corruption is controlled by the force bip-8 corruption register (register address 0f). for any bit set in this register, the corresponding bit in the calculated bip-8 is inverted before insertion into the b1 byte position. each stream has an independent fault insert register that enables the inversion of the b1 bytes. b1 bytes in all other sts-1s in the stream are filled with zeros. stream disable when disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the hsi. the hsi macro is pow- ered down on a per-stream basis, as are its lvds out- puts. scrambler the data stream is scrambled using a frame synchro- nous scrambler of sequence length 127. the scram- bling function can be disabled by software. the generating polynomial for the scrambler is 1 + x 6 + x 7 . this polynomial conforms to the standard sonet sts-12 data format. the scrambler is reset to 1111111 on the first byte of the spe (byte following the z0 byte in the twelfth sts-1). that byte and all subsequent bytes to be scrambled are exclusive ored, with the output from the byte-wise scrambler. the scrambler runs continuously from that byte on throughout the remainder of the frame. a1, a2, j0, and z0 bytes are not scrambled. stm receiver (backplane -> fpga) the ort4622 has four receiving channels that can be treated as one sts-48 stream, or treated as indepen- dent channels. incoming data is received through lvds serial ports at the data rate of 622 mbits/s. the receiver can handle the data streams with frame off- sets of up to 12 bytes. the received data streams are processed in the hsi and the stm, then passed through the cic boundary to the fpga logic.
16 lucent technologies inc. orca ort4622 fpsc advanced data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. backplane transceiver core detailed description (continued) framer block the framer block, in figure 6, takes byte-wide data from the hsi, and outputs a byte-aligned, byte-wide data stream and 8 khz sync pulse. the framer algorithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an out-of-frame (oof) state. the framer detects the a1/a2 framing pattern and generates the 8 khz frame pulse. when the framer detects oof, it will generate an interrupt. also, the framer detects an errored frame and increments an a1/a2 frame error counter. the counter can be monitored by a processor to compile performance status on the quality of the backplane. because the ort4622 is intended for use between another ort4622 or other devices via a backplane, there is only one errored frame state. thus after two transitions are missed, the state machine goes into the oof state and there is no severely errored frame (sef) or loss-of-frame (lof) indication. 5-8582 (f) figure 6. framer circuit if oof state: freeze a1 offset when = f6, or use previous offset. if ~oof state: use previous offset. data in 87 8 8 aligned compare to a1a2 transition. f628 and on success: issue 8 khz fp go to frame 8 data 8 a1 search a1a2 transition search aligned data out 8 khz fp state control counter set confirm. b1 calculate and descramble (backplane -> fpga) each rx block receives byte-wide scrambled 77.76 mhz data and a frame sync from the framer. since each hsi is independently clocked, the rx block operates on individual streams. timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. the rx block pro- duces byte-wide (optionally) descrambled data and an output frame sync for the alignment fifo block. the b1 calculation block computes a bip-8 code, using even parity over all bits of the previous sts-12 frame before descrambling and this value is checked against the b1 byte of the current frame after descrambling. a per-stream b1 error counter is incremented for each bit that is in error. the error counter may be read via the cpu interface. descrambling. the streams are descrambled using a frame synchronous descrambler of sequence length 127 with a generating polynomial of 1 + x 6 + x 7 . the section trace byte (j0) and the growth bytes (z0) are not descrambled. the descrambling function can be disabled by software. ais-l insertion. if enabled in the ais_l force register, ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream.
lucent technologies inc. 17 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. back p lane transceiver core detailed descri p tion (continued) ais-l insertion on out-of-frame. if enabled via the register ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out-of-frame condi- tion exists. internal parit y generation even parity is generated on all data bytes and is routed in parallel with the data to be checked before the pro- tection switch mux at the parallel output. fifo ali g nment ( back p lane -> fpga ) the alignment fifo allows the transfer of all data to the system clock. the fifo sync block (figure 7) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching sts-12 streams will arrive at the fpga end in perfect data sync. the frame alignment is configurable to allow for the possibility of fully independent (i.e., total frame mis- alignment) sts-12s. 5-8577 (f) fi g ure 7. interconnect of streams for fifo ali g nment the incoming data from the clock and data recovery can be separated into four sts-12 channels (a, b, c, and d). these streams can be frame aligned in the patterns shown in figure 8. 5-8575 (f) fi g ure 8. ali g nment of four sts-12 streams there is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting synchro- nization). these streams can be enabled at a later time without disrupting other streams. the fifo block consists of a 24 by 10-bit fifo per link. this fifo is used to align up to 154.3 ns of interlink skew and to transfer to the system clock. the fifo sync circuit takes metastable hardened frame pulses from the write control blocks and produces sync signals which indicate when the read control blocks should begin reading from the first fifo location. on top of the sync signals this block produces an error indicator which indicates that the sig- nals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). sync and error signals are sent to read control block for alignment. the read control block is synched only once on start-up, any further synchroni- zation is s/w controlled. the action of resynching a read control block will always cause a data hit. a s/w register allows the read control block to be resynched. sts-12 stream a sts-12 stream b sts-12 stream c sts-12 stream d fifo sync stream a stream b stream c stream d stream a stream b stream c stream d
18 18 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. backplane transceiver core detailed description (continued) link alignment. the general operation of the link alignment algorithm is to wait 12 clocks (i.e., half the fifo) from the arriving frame pulse and then signal the read control block to begin reading. for perfectly aligned frame pulses across the links, it is simply a matter of counting down 12 and then signaling the read control block. the algorithm down counts by one until all of the frame pulses have arrived and then by two when they are all present. for example (figure 9), if all pulses arrive together then alignment algorithm would count 24 (12 clocks); if, however, the arriving pulses are spread out over four clocks, then it would count one for the first four pulses and then two per clock afterward which gives a total of 14 clocks between first frame pulse and the first read. this puts the center of arriving frame pulses at the halfway point in the buffer. this is the extent of the algorithm and it has no facility for actively correcting problems once they occur. the write control block receives byte-wide data at 77.76 mhz and a frame pulse two clocks before the first a1 byte of the sts-12 frame. it generates the write address for the fifo block. the first a1 in every sts- 12 stream is written in the same location (address 0) in the fifo. also, a frame bit is passed through the fifo along with the first byte before the first a1 of the sts- 12. the read control block synchronizes the reading of the fifo for streams that are to be aligned. reading begins when the fifo sync signals that all of the appli- cable a1s and the appropriate margin have been writ- ten to the fifo. all of the read blocks to be synchronized begin reading at the same time and same location in memory (address 0). the alignment algorithm takes the difference between read address and write address to indicate the relative clock alignments between sts-12 streams. if this depth indication exceeds certain limits (12 clocks), then an interrupt is given to the microprocessor (alignment overflow). each sts-12 stream can be realigned by software if it gets too far out of line (this would cause a data hit). 5-8584 (f) figure 9. examples of link alignment pointer mover block (backplane -> fpga) the pointer mover maps incoming frames to the line framing that is supplied by the fpga logic. the k1/k2 bytes and h1-ss bits are also passed through to the pointer generator so that the fpga can receive them. the pointer mover handles both concatenations inside the sts-12, and to other sts-12s inside the core. 24-byte fifo 24-byte fifo all fps 12 clocks sync. pulse arrive together (writing begins) (reading begins) sync. pulse (reading begins) last fp arrives 4 clocks first fp arrives (writing begins) 10 clocks perfectly aligned frames 4-byte spread in arriving frames
lucent technologies inc. 19 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. backplane transceiver core detailed description (continued) the pointer mover block can correctly process any length of concatenation of sts frames (multiple of three) as long as it begins on an sts-3 boundary (i.e., sts-1 number one, four, seven, 10, etc.) and is contained within the smaller of sts-3, 12, or 48. see details in table 2. table 2 . valid starting positions for an sts-mc sts-1 number sts-3cspe sts-6cspe sts-9cspe sts-12cspe sts-15cspe sts-18c to sts-48c spes 1 yes yes yes yes yes yes 4 yes yes yes no yes 7 yes yes no no yes 10 yes no no no yes 13 yes yes yes yes yes 16 yes yes yes no yes 19 yes yes no no yes 22 yes no no no yes 25 yes yes yes yes yes 28 yes yes yes no yes 31 yes yes no no yes 34 yes no no no yes no 37 yes yes yes yes no no 40 yes yes yes no no no 43 yes yes no no no no 46 yes no no no no no note: yes = sts-mc spe can start in that sts-1. no = sts-mc spe cannot start in that sts-1. = yes or no, depending on the particular value of m. pointer interpreter state machine. the pointer inter- preters highest priority is to maintain accurate dataflow (i.e., valid spe only) into the elastic store. this will ensure that any errors in the pointer value will be cor- rected by a standard, fully sonet compliant, pointer interpreter without any data hits. this means that error checking for increment, decrement, and new data flag (ndf) (i.e., eight of 10) are maintained in order to ensure accurate dataflow. a single valid pointer (i.e., 0782) that differs from the current pointer will be ignored. two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the j1 location to the latest pointer value (the generator will then produce an ndf). this block is designed to han- dle single bit errors without affecting dataflow or chang- ing state. the pointer interpreter has only three states (norm, ais, and conc). norm state will begin whenever two consecutive norm pointers are received. if two con- secutive norm pointers are received that both differ from the current offset, then the current offset will be reset to the last received norm pointer. when the pointer interpreter changes its offset it causes the pointer generator to receive a j1 value in a new posi- tion. when the pointer generator gets an unexpected j1 it resets its offset value to the new location and declares an ndf. the interpreter is only looking for two consecutive pointers that are different from the current value. these two consecutive norm pointers do not have to have the same value. for example, if the cur- rent pointer is ten and a norm pointer with offset of 15 and a second norm pointer with offset of 25 are received, then the interpreter will change the current pointer to 25. the receipt of two consecutive conc pointers causes conc state to be entered. once in this state offset values from the head of the concatena- tion chain are used to determine the location of the sts spe for each sts in the chain. two consecutive ais pointers cause the ais state to occur. any two con- secutive normal or concatenation pointers will end this ais state. this state will cause the data leaving the pointer generator to be overwritten with 0xff.
20 lucent technologies inc. orca ort4622 fpsc advanced data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. backplane transceiver core detailed description (continued) 5-8589 (f) figure 10. pointer mover state machine norm conc ais 2 x c on c 2 x n or m 2 x n or m 2 x a i s 2 x conc 2 x ais pointer generator. the pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream. the generator also creates offset pointers based on the location of the j1 byte as indicated by the pointer interpreter. the generator will signal ndfs when the interpreter signals that it is com- ing out of ais state. the pointer generator resets the pointer value and generates ndf every time a byte marked j1 is read from the elastic store that doesnt match the previous offset. increment and decrement signals from the pointer interpreter are latched once per frame on either the f1 or e2 byte times (depending on collisions), this ensures constant values during the h1 through h3 times. the choice of on which byte time to do the latching is made once when the relative frame phases (i.e., received and system) are determined. this latch point is then stable unless the relative framing changes and the received h byte times collide with the system f1 or e2 times in which case the latch point would be switched to the collision free byte time. there is no restriction on how many or how often incre- ments and decrements are processed. any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. the responsibility for meeting the sonet criteria for max frequency of pointer adjustments is left to an upstream pointer pro- cessor. when the interpreter signals an ais state, the genera- tor will immediately begin sending out 0xff in place of data and h1, h2, h3. this will continue until the inter- preter returns to norm or conc (pointer mover state machine) states and a j1 byte is received. transport overhead extraction transport overhead is extracted from the receive data stream by the toh extract block. the incoming data gets loaded into a 36-byte shift register on the system clock domain. this in turn is clocked onto the toh clock domain at the start of the spe time, where it can be clocked out. during the spe time, the receiver toh frame pulse is generated, rx_toh_fp, which indicates the start of the row of 36 toh bytes. this pulse, along with the receive toh clock enable, rx_toh_ck_en, as well as the toh data, are all launched on the rising edge of the toh clock toh_clk. special toh byte functions k1 and k2 handling. k1 and k2 bytes can be option- ally passed through the pointer mover under software control, or can set to zero with the other toh bytes. a1 and a2 handling. a1 and a2 bytes are always regenerated and set to hexadecimal f6 and 28, respectively.
lucent technologies inc. 21 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. backplane transceiver core detailed description (continued) spe and c1j1 outputs . these two signals for each channel are passed to the fpga logic to allow a pointer pro- cessor or other function to extract payload without interpreting the pointers. for the ort4622, each frame has 12 sts-1s. in the spe region, there are 12 j1 pulses for each sts-1s. there is one c1(j0) pulse in the toh area for one frame since all 12 sts-1s share the same row of toh. thus, there is a total of 12 j1 pulses and one c1(j0) pulse per frame. c1(j0) pulse is coincident with the j0 of sts1 #1. in each frame, the spe flag is active when the data stream is in spe area. spe behavior is dependent on pointer movement and concatenation. note that in the toh area, h3 can also carry valid data. when valid spe data is carried in this h3 slot, spe is high in this particular toh time slot. in the spe region, if there is no valid data during any spe column, the spe signal will be set to low. spe allow a pointer processor to extract payload without interpreting the pointers. the spe and c1j1 functionality are described in table 3. table 3 . spe and c1j1 functionality note: the following rules must be observed for generating spe and c1j1 signals: on occurrence of ais-p on any of the sts-1, the re must be no corresponding j1 pulse. in case of concatenated payloads (up to sts48c), only the head sts-1 of the group must have an assoc iated j1 pulse. c1j1 signal must track any pointer movements. during a negative justification event, spe must be set high during the h3 byte to indicate that payload data is available. during a positive justification event, spe must be set low during the positive stuf f opportunity byte to indicate that payload data is not available. spe c1j1 description 0 0 toh information excluding c1(j0) of sts1 #1 0 1 position of c1(j0) of sts1 #1 1 0 spe information excluding the 12 j1 bytes 1 1 position of the 12 j1 bytes powerdown mode powerdown mode will be entered when the corre- sponding channel is disabled. channels can be inde- pendently enabled or disabled under software control. parallel data bus output enable and toh serial data output enable signals are made available to the fpga logic. the outputs can be 3-stated when the corre- sponding channel is disabled. the hsi macrocells cor- responding channel is also powered down. the device will power up with all four channels in powerdown mode. in addition, an lvds_en pin has been added to control the lvds pins during boundary scan. during functional operation, enabling/disabling lvds buffers is con- trolled by software registers. when in boundary scan mode, lvds_en controls the enabling/disabling of lvds buffers instead of software registers. this lvds_en pin should be pulled high on the board for functional operation, and pulled low during boundary scan. redundancy and protection switching the ort4622 supports sts-12/sts-48 redundancy by either software or hardware control for protection switching applications. for the transmitter mode, no additional functionality is required for redundant opera- tion. for receiving data, sts-12 data redundancy can be implemented within the same device; while sts-48 data stream requires multiple devices to support redun- dancy. in sts-12 mode, the channel a receive data bus port is used for both channel a and channel b. similarly, the channel c receive data bus port is used for both chan- nel c and channel d. channel b and channel d become the redundant channels. the channel b and channel d receive data bus ports are unused. soft reg- isters provide independent control to the protection switching muxes for both parallel data ports and serial toh data ports. when direct hardware control for pro- tection switching is needed, external protection switch pins are available for channels a and b, and also chan- nels c and d. the hardware redundancy only supports parallel spe/toh data protection switching, but not the serial toh data. in sts-48 mode, both parallel and serial port output pins on the fpga side should be 3-stated if two or more devices are tied to the appropriate data bus. the existing local bus enable signals at the cic can be used as 3-state controls if needed, which can be easily accessed by software control. users can also create their own protection switch 3-state enable signals either in fpga logic or, external to the device, depend- ing on the specific application.
22 lucent technologies inc. orca ort4622 fpsc advanced data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. memory map definition of register types there are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. there are no mixed registers in the chip. this means that all bits of a particular register (particular address) are structurally the same. table 4 . structural register elements element register description sreg status register a status register is read only, and, as the name implies, is used to convey the status information of a particular element or function of the ort4622 core. the reset value of an sreg is really the reset value of the particular element or function that is being read. in some cases, an sreg is really a fixed value. an example of which is the fixed id and revision registers. creg control register a control register is read and writable memory element inside core control. the value of a creg will always be the value written to it. events inside the ort4622 core cannot effect creg value. the only exception is a soft reset, in which case the creg will return to its default value. the control register have default values as defined in the default value column of table 5, memory map. preg pulse register each element, or bit, of a pulse register is a control or event signal that is asserted and then deasserted when a value of one is written to it. this means that each bit is always of value 0 until it is written to, upon which it is pulsed to the value of one and then returned to a value of 0. a pulse register will always have a read value of 0. iareg interrupt alarm register each bit of an interrupt alarm register is an event latch. when a particular event is produced in the ort4622 core, its occurrence is latched by its associated iareg bit. to clear a particular iareg bit, a value of one must be written to it. in the ort4622 core, all iareg reset values are 0. isreg interrupt status register each bit of an interrupt status register is physically the logical or function. it is a consolidation of lower level interrupt alarms and/or isreg bits from other registers. a direct result of the fact that each bit of the isreg is a logical or function means that it will have a read value of one if any of the consolidation signals are of value one, and will be of value 0 if and only if all consolidation signals are of value 0. in the ort4622 core, all iareg default values are 0. ereg interrupt enable register each bit of a status register or alarm register has an associated enable bit. if this bit is set to value one, then the event is allowed to propagate to the next higher level of consolidation. if this bit is set to zero, then the associated iareg or isreg bit can still be asserted but an alarm will not propagate to the next higher level. an interrupt enable bit is an interrupt mask bit when it is set to value 0. registers access and general description the memory map comprises three address blocks: n generic register block: id, revision, scratch pad, lock, fifo alignment, and reset registers. n device register block: control and status bits, com- mon to the four channels. n channel register blocks: each of the four channels have an address block. the four address blocks have the exact same structure with a constant address offset between channel register blocks. all registers are write-protected by the lock register, except for the scratch pad register. the lock register is a 16-bit read/write register. write access is given to registers only when the key value 0xa001 is present in the lock register. an error flag will be set upon detecting a write access when write permission is denied. the default value is 0x0000. after powerup reset or soft reset, unused register bits will be read as zeros. unused address locations are also read as zeros. write only register bits will be read as zeros. the detailed information on register access and function are described on the tables, memory map, and memory map bit description.
lucent technologies inc. 23 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. memory map (continued) memory map overview table 5 . memory map addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes generic register block 00 sreg fixed id msb [7:0] a0 1 01 sreg fixed id lsb [7:0] 01 02 sreg fixed rev [7:0] 01 03 creg scratch pad [7:0] 00 04 creg lockreg msb [7:0] 00 05 creg lockreg lsb [7:0] 00 06preg fifo align- ment command global reset command na device register block 08 creg rx toh frame and rx toh clock enable hi-z control ext prot sw en ext prot sw function sts-48 sts-12 sel lvds lpbk control 00 2 09 creg parallel port out- put mux select for ch c parallel port out- put mux select for ch a serial port output mux select for ch c serial port output mux select for ch a 0f 0a creg fifo aligner threshold value (min) [4:0] 02 0b creg fifo aligner threshold value (max) [4:0] 15 0c creg scrambler/ descram- bler control input/ output parallel bus parity control line lpbk control number of consecutive a1/a2 errors to generate [3:0] 60 3 0d creg a1 error insert value [7:0] 00 0e creg a2 error insert value [7:0] 00 0f creg transmitter b1 error insert mask [7:0] 00 notes: 1. generic register block. 2. device register block-rx. 3. device register block-tx.
24 24 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. device register block (continued) 10 isreg per device int ch d interrupt ch c interrupt ch b interrupt ch a interrupt 00 4 11 iereg enable/mask register [4:0] 00 12iareg write to locked register error flag frame offset error flag 00 13iereg enable/mask register [1:0] 00 channel register block 20, 38, 50, 68 * creg hi-z control of toh data output hi-z control of parallel output bus channel enable/ disable control parallel output bus parity err ins cmd rx k1/k2 source select toh serial output port par err ins cmd force ais-l control rx behavior in lof 01 5 21, 39, 51, 69 creg tx mode of opera- tion tx e1 f1 e2 source select tx s1 m0 source select tx k1/k2 source select tx d12 source select tx d11 source select tx d10 source select tx d9 source select 00 6 22, 3a, 52, 6a creg tx d8 source select tx d7 source select tx d6 source select tx d5 source select tx d4 source select tx d3 source select tx d2 source select tx d1 source select 00 23, 3b, 53, 6b creg b1 error insert command a1/a2 error ins command 00 24, 3c, 54, 6c sreg concat indication 12 concat indication 9 concat indication 6 concat indication 3 na 7 25, 3d, 55, 6d sreg concat indication 11 concat indication 8 concat indication 5 concat indication 2 concat indication 10 concat indication 7 concat indication 4 concat indication 1 na addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes memory map (continued) table 5. memory map (continued) notes: 1. generic register block. 2. device register block-rx. 3. device register block-tx. 4. top level interrupts. 5. rx control. 6. tx control signals. 7. per sts#1 cos flag. * addr values delimited by a comma indicate the address for each of 4 channels, from channel a to d. for example, the register t o tx control sig- nals has addresses of 20, 38, 50, and 68. this indicates that channel a tx control signals are at address 20, channel b tx cont rol signals are at address 38, channel c tx control signals are at address 50, and channel d tx control signals are at address 68.
lucent technologies inc. 25 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. channel re g ister block (continued) 26, 3e, 56, 6e isreg elastic store overflow flag ais-p flag per sts-12 alarm flag 00 8 27, 3f, 57, 6f iereg enable/mask register [2:0] 00 28, 40, 58, 70 iareg toh serial input port parity error flag input parallel bus parity error flag lvds link b1 parity error flag lof flag receiver internal path parity error flag fifo aligner threshold error flag 00 9 29,41, 59, 71 iereg enable/mask register [5:0] 00 2a, 42, 5a, 72 iaregais interrupt flags 12 ais interrupt flag 9 ais interrupt flag 6 ais interrupt flags 3 00 10 2b, 43, 5b, 73 iareg ais interrupt flag 11 ais interrupt flag 8 ais interrupt flag 5 ais interrupt flag 2 ais interrupt flag 10 ais interrupt flag 7 ais interrupt flag 4 ais interrupt flag 1 00 2c, 44, 5c, 74 iereg enable/ mask ais interrupt flag 12 enable/ mask ais interrupt flag 9 enable/ mask ais interrupt flag 6 enable/ mask ais interrupt flag 3 00 2d, 45, 5d, 75 iereg enable/ mask ais interrupt flag 11 enable/ mask ais interrupt flag 8 enable/ mask ais interrupt flag 5 enable/ mask ais interrupt flag 2 enable/ mask ais interrupt flag 10 enable/ mask ais interrupt flag 7 enable/ mask ais interrupt flag 4 enable/ mask ais interrupt flag 1 00 2e, 46, 5e, 76 iareges overflow flag 12 es overflow flag 9 es overflow flag 6 es overflow flag 3 00 addr [6:0] re g . t y pe db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes memor y ma p (continued) table 5. memor y ma p (continued) notes: 1. generic register block. 2. device register block-rx. 3. device register block-tx. 4. top level interrupts. 5. rx control. 6. tx control signals. 7. per sts#1 cos flag. 8. per channel interrupt. 9. per stsC12 interrupt flags. 10. per stsC1 interrupt flags.
26 26 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. channel register block (continued) 2f, 47, 5f, 77 iareg es overflow flag 11 es overflow flag 8 es overflow flag 5 es overflow flag 2 es overflow flag 10 es overflow flag 7 es overflow flag 4 es overflow flag 1 00 10 30, 48, 60, 78 iereg enable/ mask es overflow flags 12 enable/ mask es overflow flag 9 enable/ mask es overflow flags 6 enable/ mask es overflow flags 3 00 31, 49, 61, 79 iereg enable/ mask es overflow flag 11 enable/ mask es overflow flag 8 enable/ mask es overflow flag 5 enable/ mask es overflow flag 2 enable/ mask es overflow flag 10 enable/ mask es overflow flag 7 enable/ mask es overflow flag 4 enable/ mask es overflow flag 1 00 32, 4a, 62, 7a counter overflow lvds link b1 parity error counter 00 11 33, 4b, 63, 7b counter overflow lof counter 00 34, 4c, 64, 7c counter overflow a1/a2 frame error counter 00 addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes memory map (continued) table 5. memory map (continued) notes: 1. generic register block. 2. device register block-rx. 3. device register block-tx. 4. top level interrupts. 5. rx control. 6. tx control signals. 7. per sts#1 cos flag. 8. per channel interrupt. 9. per stsC12 interrupt flags. 10. per stsC1 interrupt flags. 11. binning.
lucent technologies inc. 27 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. table 6 . memor y ma p bit descri p tions bit/register name(s ) bit/ register location (hex) register type default value (hex) description generic re g ister block fixed id msb [7:0] fixed id lsb [7:0] fixed rev [7:0] 00 [7:0] 01 [7:0] 02 [7:0] sreg a0 01 01 scratch pad [7:0] 03 [7:0] creg 00 the scratch pad has no function and is not used anywhere in the ort4622 core. however, this register can be written to and read from. lockreg msb [7:0] lockreg lsb [7:0] 04 [7:0] 05 [7:0] creg 00 00 in order to write to registers in memory locations 06 to 7f, lockreg msb and lockreg lsb must be respectively set to the values of a0 and 01. if the msb and lsb lockreg values are not set to {a0, 01}, then any val- ues written to the registers in memory locations 06 to 7f will be ignored. after reset (both hard and soft) the ort4622 core is in a write locked mode. the ort4622 core needs to be unlocked before it can be written to. also note that the scratch pad register (03) can always be written to as it is unaffected by write lock mode. fifo alignment command global reset command 06 [0] 06 [1] preg na the fifo alignment and global reset commands are both accessed via the pulse register in memory address 06. the fifo alignment com- mand is used to frame align the outputs of the four receive stm stream fifos. the global reset command is a soft (software initiated) reset. nevertheless, the global reset command will have the exact reset effect as a hard (rst_n pin) reset. device re g ister block lvds lpbk control 08 [0] creg 0 0 no loopback. 1 lvds loopback, transmit to receive on. sts48 sts12 sel 08 [1] creg 0 this control signal is untracked in the ort4622 core. it is a scratch bit, and its value has no effect on the ort4622 core. ext prot sw en ext prot sw func 08 [3:2] creg 0 ext prot sw en ext prot sw func switching control master. 0 mux is controlled by software (one control bit per mux). output buffers are controlled by software (one control bit per channel). 1 0 mux on parallel output bus of channel a is controlled by prot_switch a/b pin (0-> channel a, 1-> channel b). mux on parallel output bus of channel c is controlled by prot_switch c/d pin (0 -> channel c, 1-> channel d). output buffers are controlled by software (one control bit per channel). 1 1 mux is controlled by software (one control bit per mux). output buffers on parallel output bus of channels a and b are controlled by prot_switch a/b pin (0-> buffers active, 1-> hi-z). output buffers on parallel output bus of channels c and d are controlled by prot_switch c/d pin (0 -> buffers active, 1-> hi-z). memor y ma p (continued) memory map bit descriptions
28 28 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. device register block (continued) rx toh frame and rx toh clock enable hi-z control 08 [4] creg 0 0 hi-z . 1 enable receive toh clk and fp outputs. serial port output mux select for channel a serial port output mux select for channel c parallel port output mux select for channel a parallel port output mux select for channel c 09 [0] 09 [1] 09 [2] 09 [3] creg 1 1 1 1 serial port output mux select for channel 1 0 toh output one is multiplexed to channel b. 1 toh output one is multiplexed to channel a. serial port output mux select for channel 3 0 toh output three is multiplexed to channel d. 1 toh output three is multiplexed to channel c. parallel port output mux select for channel 1 0 parallel output data bus one is multiplexed to channel b. 1 parallel output data bus one is multiplexed to channel a. parallel port output mux select for channel 3 0 parallel output data bus three is multiplexed to channel d. 1 parallel output data bus three is multiplexed to channel c. fifo aligner thresh- old value (min) [4:0] fifo aligner thresh- old value (max) [4:0] 0a [4:0] 0b [4:0] creg 02 15 these are the minimum and maximum thresholds values for the per channel receive direction alignment fifos. if and when the minimum or maximum threshold value is violated by a particular channel, then the interrupt event fifo aligner threshold error will be generated for that channel and latched as a fifo aligner threshold error flag in the respective per sts-12 interrupt alarm register. the allowable range for minimum threshold values is 0 to 23. the allowable range for maximum threshold values is 0 to 22. note that the minimal and maximum fifo aligner threshold values apply to all four channels. number of consecu- tive a1/a2 errors to generate [3:0] a1 error insert value [7:0] a2 error insert value [7:0] 0c [7:0] 0d [7:0] 0e [7:0] creg 00 00 00 these three per device control signals are used in conjunction with the per channel a1/a2 error insert command control bits to force a1/a2 errors in the transmit direction. if a particular channels a1/a2 error insert command control bit is set to the value one then the a1 and a2 error insert values will be inserted into that channels respective a1 and a2 bytes. the number of consecutive frames to be corrupted is determined by the number of consecutive a1, a2 errors to generate[3:0] control bits. the error insertion is based on a rising edge detector. as such, the con- trol must be set to value 0 before trying to initiate a second a1/a2 cor- ruption. line lpbk control 0c [4] creg 0 0 no loopback. 1 receive to transmit loopback on fpga side. input/output parallel bus parity control 0c [5] creg 0 0 even parity. 1 odd parity. bit/register name(s ) bit/ register location (hex) register type default value (hex) description memory map (continued) table 6. memory map bit descriptions (continued)
lucent technologies inc. 29 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. device re g ister block (continued) scrambler/ descrambler control 0c [6] creg 1 0 no receive direction descramble/transmit direction scramble. 1 in receive direction descramble channel after sonet frame recovery. in transmit direction scramble data just before parallel to serial conversion. transmit b1 error insert mask [7:0] 0f [7:0] creg 00 0 no error insertion. 1 invert corresponding bit in b1 byte. channel a int channel b int channel c int channel d int per device int enable/mask register [4:0] 10 [0] 10 [1] 10 [2] 10 [3] 10 [4] 11 [4:0] creg creg creg creg creg iereg 0 0 0 0 0 0 consolidation interrupts 0 no interrupt. 1 interrupt. frame offset error flag write to locked register error flag enable/mask register [1:0] 12 [0] 12 [1] 13 [1:0] iareg iareg iereg 0 0 0 if in the receive direction the phase offset between any two channels exceeds 17 bytes, then a frame offset error event will be issued. this condition is continuously monitored. if the ort4622 core memory map has not been unlocked (by writing a1 00 to the lock registers), and any address other than the lockreg reg- isters or scratch pad register is written to, then a write to locked register event will be generated. channel re g ister block rx behavior in lof force ais-l control 20 38 50 68 [0] 20 38 50 68 [1] 1 0 receive behavior in log 0 when receive direction oof occurs, do not insert ais-l. 1 when receive direction oof occurs, insert ais-l. force ais-1 control 0 do not force ais-l. 1 force ais-l. toh serial output port par err ins cmd 20 38 50 68 [2] 0 0 do not insert a parity error. 1 insert parity error in parity bit of receive toh serial output for as long as this bit is set. rx k1/k2 source select 20 38 50 68 [3] 0 0 set receive direction k1/k2 bytes to 0. 1 pass receive direction k1/k2 though pointer mover. parallel output bus parity err ins cmd 20 38 50 68 [4] 0 0 do not insert parity error. 1 insert parity error in the parity bit of receive direction parallel out- put bus for as long as this bit is set. bit/register name(s ) bit/ register location (hex) register type default value (hex) description memor y ma p (continued) table 6. memor y ma p bit descri p tions (continued)
30 30 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. channel register block (continued) channel enable/ disable control hi-z control of parallel output bus hi-z control of toh data output 20, 38, 50, 68 [5] 20, 38, 50, 68 [6] 20, 38, 50, 68 [7] creg creg creg 0 0 0 channel enable/disable control 0 powerdown channel and 3-state output buses. 1 functional mode. hi-z control of parallel output bus 0 3-state output bus. 1 functional mode. hi-z control of toh data output 0 3-state output lines. 1 functional mode. tx mode of operation tx e1 f2 e2 source select tx s1 m0 source select tx k1 k2 source select tx d12d9 source select tx d8d1 source select 21, 39, 51, 69 [7] 21, 39, 51, 69 [6] 21, 39, 51, 69 [5] 21, 39, 51, 69 [4] 21, 39, 51, 69 [3:0] 22, 40, 52, 70 [7:0] creg creg creg creg creg creg 0 0 0 0 4h0 8h00 transmit mode of operation 0 insert toh from serial ports. 1 pass through all toh. other registers 0 insert toh from serial ports. 1 pass through that particular toh byte. a1/a2 error insert command b1 error insert command 23, 3b, 53, 6b [0] 23, 3b, 53, 6b [1] creg creg 0 0 0 do not insert error * . 1 insert error for number of frames in register hex 0c * . 0 do not insert error ? . 1 insert error for one frame in b1 bits defined by register hex 0f ? . concat indication 12, 9, 6, 3 concat indication 11, 8, 5, 2, 10, 7, 4, 1 24, 3c, 54, 6c [3:0] 25, 3d, 55, 6d [7:0] sreg sreg 0 0 the value one in any bit location indicates that sts# is in concat mode. a 0 indicates that the sts in not in concat mode, or is the head of a concat group. per stsC12 alarm flag ais-p flag elastic store overflow flag enable/mask register [2:0] 26, 3e, 56, 6e [0] 26, 3e, 56, 6e [1] 26, 3e, 56, 6e [2] 27, 3f, 57, 6f [3] isreg isreg isreg iereg 0 0 0 3b000 these flag register bits per sts-12 alarm flag, ais-p flag, and elastic store overflow flag are the per-channel interrupt status (consolidation) register. bit/register name(s ) bit/ register location (hex) register type default value (hex) description memory map (continued) table 6. memory map bit descriptions (continued) * the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a second a1/a2 corruption. ? the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a second b1 corruption.
lucent technologies inc. 31 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. channel re g ister block (continued) fifo aligner threshold error flag receiver internal path parity error flag lof flag lvds link b1 parity error flag input parallel bus parity error flag toh serial input port parity error flag enable/mask register [5:0] 28, 40, 58, 70 [0] 28, 40, 58, 70 [1] 28, 40, 58, 70 [2] 28, 40, 58, 70 [3] 28, 40, 58, 70 [4] 28, 40, 58, 70 [5] 28, 40, 58, 70 [6] iareg iareg iareg iareg iareg iareg iareg 0 0 0 0 0 0 6h00 these are per the sts-12 alarm flags. ais interrupt flags 12, 9, 6, 3 ais interrupt flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 29, 41, 59, 71[3:0] 2a, 42, 5a, 72 [7:0] 2b, 43, 5b, 73[3:0] 2c, 44, 5c, 74 [7:0] iareg iareg iereg iereg 4h0 8h00 4h0 8h00 these are the ais-p alarm flags. es overflow flags 12, 9, 6, 3 es overflow flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2d, 45, 5d, 75 [3:0] 2e, 46, 5e, 76 [7:0] 2f, 47, 5f, 77 [3:0] 30, 48, 60, 78 [7:0] 4h0 8h00 4h0 8h00 these are the elastic store overflow alarm flags. lvds link b1 parity error counter 31, 49, 61, 79 [7:0] counter 8h00 7-bit count + overflow-reset on read. lof counter 32, 4a, 62, 7a [7:0] counter 8h00 7-bit count + overflow-reset on read. a1/a2 frame error counter 33, 4b, 63, 7b [7:0] counter 8h00 7-bit count + overflow-reset on read. bit/register name(s ) bit/ register location (hex) register type default value (hex) description memor y ma p (continued) table 6. memor y ma p bit descri p tions (continued)
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 32 lucent technologies inc. lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 3+ fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 7 . absolute maximum ratings recommend operating conditions table 8 . recommend operating conditions symbol parameter min max unit t stg storage temperature 65 150 c v dd supply voltage with respect to ground 0.5 7.0 v input signal with respect to ground 0.5 v dd + 0.3 v signal applied to high-impedance output 0.5 v dd + 0.3 v maximum package body temperature 220 c ort4622 temperature range (ambient) temperature range (junction) i/o supply voltage (v dd ) internal supply voltage (v dd 2) C40 c to +85 c C40 c to +125 c 3.135 v to 3.465 v 2.3 v to 2.7 v
lucent technologies inc. 33 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. electrical characteristics table 9 . electrical characteristics for fpga i/o ort4622 industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.3 v to 2.7 v, C40 c < t a < +85 c . * on the series 3 devices, the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . symbol parameter test conditions ort4622 unit min max v ih v il input voltage: high low input configured as cmos (clamped to v dd ) 50% v dd gnd C 0.5 v dd + 0.3 30% v dd v v v ih v il input voltage: high low input configured as 5 v tolerant 50% v dd gnd C 0.5 5.8 30% v dd v v v oh v ol output voltage: high low v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 v v i l input leakage current v dd = max, v in = v ss or v dd C10 10 a i ddsb standby current (t a = 25 c, v dd = 3.3 v, v dd 2 = 2.5 v) internal oscillator running, no output loads, inputs at v dd or gnd (after configuration) 5.3ma i ddsb standby current (t a = 25 c, v dd = 3.3 v, v dd 2 = 2.5 v) internal oscillator stopped, no output loads, inputs at v dd or gnd (after configuration) 1.4ma v dr data retention voltage t a = 25 c2.3v i pp powerup current power supply current at approximately 1 v, within a recommended power supply ramp rate of 1 ms200 ms 2.7 ma c in input capacitance (t a = 25 c, v dd = 3.3 v, v dd 2 = 2.5 v) test frequency = 1 mhz 8pf c out output capacitance (t a = 25 c, v dd = 3.3 v, v dd 2 = 2.5 v) test frequency = 1 mhz 9pf r done done pull-up resistor* 100 k w r m m[3:0] pull-up resistors* 100 k w i pu i/o pad static pull-up current* (v dd = 3.6 v, v in = v ss , t a = 0 c) 14.4 50.9 a i pd i/o pad static pull-down current (v dd = 3.6 v, v in = v ss, t a = 0 c) 26 103 a r pu i/o pad pull-up resistor* v dd = all, v in = v ss , t a = 0 c 100 k w r pd i/o pad pull-down resistor v dd = all, v in = v dd , t a = 0 c 50 k w
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 34 lucent technologies inc. lucent technologies inc. electrical characteristics (continued) table 10 . electrical characteristics for embedded core i/o other than lvds i/o note: all outputs are driving 35 pf, except cpu data bus pins which drive 100 pf. it is assumed that the ttl buffers from the standard-cell library can handle the 100 pf load. symbol parameter min max unit v ih input high voltage (ttl input) 2.0 5.5 v v il input low voltages (ttl input) 0.8 v v oh output high voltage (ttl output) 2.4 v v oh output low voltage (ttl output) 0.4 v
lucent technologies inc. 35 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. hsi circuit specifications input data the 622 mbits/s scrambled input data stream must conform to sonet sts-12 and sdh stm-4 data format using either a pn7 or pn9 sequence. the pn7 characteristic is 1 + x 6 + x 7 and the pn9 characteristic is 1 + x 4 + x 9 . the longest allowable stream of nontransitional 622 mbits/s input data is 60 bits. this sequence should not occur more often than once per minute. an input signal phase change of no more than 100 ps is allowed over 200 ns time interval, which translates to a frequency change of 500 ppm. the signal eye opening must be greater than 0.4 uip-p and the unit interval for 622 mbits/s is 1.6075 ns. jitter tolerance the input jitter tolerance of the ort4622 is shown in table 11. table 11 . jitter tolerance generated output jitter the generated output jitter is a maximum of 0.2 uip-p from 250 khz to 5 mhz. pll pll requires an external 10 k w pull-down resistor. table 12 . pll input reference clock table 13 . input reference clock frequency uip-p 250 khz 0.6 25 khz 6.0 2 khz 60 parameter min max unit loop bandwidth 6 mhz jitter peaking 2 db powerup reset duration 10 s lock acquisition 1 ms parameter min max frequency deviation 20 ppm frequency change 500 ppm phase change in 200 ns 100 ps
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 36 lucent technologies inc. lucent technologies inc. l vds i/o table 14. lvds driver dc data* * external reference, ref10 = 1.0 v 3%, ref14 = 1.4 v 3% table 15 . lvds driver ac data symbol parameter test conditions min typ max unit v oh driver output voltage high, v oa or v ob r load = 100 w 1% 1.475* v v ol driver output voltage low, v oa or v ob r load = 100 w 1% 0.925* v v od driver output differential voltage v od = (v oa C v ob ) (with external reference resistor) r load = 100 w 1% 0.25 0.45* v v os driver output offset voltage v os = (v oa + v ob )/2 r load = 100 w 1% 1.125* 1.275* v r o output impedance, single ended v cm = 1.0 v and 1.4 v 40 50 60 w delta r o r o mismatch between a and b v cm = 1.0 v and 1.4 v 10 % change in |v od | between 0 and 1 r load = 100 w 1% 25 mv change in |v os | between 0 and 1 r load = 100 w 1% 25 mv i sa, i sb output current driver shorted to ground 24ma i sab output current drivers shorted together 12ma |xa|, |xb| power-off output leakage v dd = 0 v v pa d , v pa d n = 0 C 3 v 30 a symbol parameter test conditions min max unit t fall v od fall time, 80% to 20% z load = 100 w 1% c pa d = 3.0 pf, c pa d = 3.0 pf 100 200 ps t rise v od rise time, 20% to 80% z load = 100 w 1% c pa d = 3.0 pf, c pa d = 3.0 pf 100 200 ps t skew1 differential skew |tphlaCtplhb| or |tphlbCtplha| any differential pair on package at 50% point of the transition 50ps t skew2 channel-to-channel skew |tpdiffmCtpdiffn|, any two signals on package at 0 v differential ps t plh t phl propagation delay time z load = 100 w 1% c pa d = 3.0 pf, c padn = 3.0 pf 0.50 0.55 0.90 1.03 ps
lucent technologies inc. 37 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. lvds i/o (continued) lvds receiver buffer requirements table 16 . lvds receiver dc data * buffer will not produce output transition when input is open-circuited. note: v dd = 3.1v3.5 v, 0 c 125 c , slow-fast process. table 17 . lvds receiver ac data table 18 . lvds receiver power consumption table 19. lvds operating parameters note: under worst-case operating condition, the lvds driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when outputs are short-circuited to each other or to ground, the lvds will not suffer permanent damage. symbol parameter test conditions min typ max unit v i receiver input voltage range, v ia or v ib |v gpd | < 925 mvdc 1 mhz 0 1.2 2.4 v |v idth | receiver input differential threshold |v gpd | < 925 mv 400 mhz C100 100 mv v hyst receiver input differential hysteresis v idthh C v idthl *mv r in receiver differential input impedance with built-in termination, center-tapped 80 100 120 w symbol parameter test conditions min max unit t pwd receiver output pulse-width distortion |v idth | = 100 mv 311 mhz tbdps t plh , t phl propagation delay time c l = 1.5 pf 0.75 0.74 1.65 1.82 ns with common-mode variation, (0 v to 2.4 v) c l = 1.5 pf 50 ps t rise receiver output signal rise time, v od 20% to 80% c l = 1.5 pf 150 350 ps t fall receiver output signal fall time, v od 80% to 20% c l = 1.5 pf 150 350 ps symbol parameter test conditions min max unit pr dc receiver dc power dc 34.8 mw pr ac receiver ac power ac, c l = 1.5 pf 0.026 mw/mhz parameter test conditions min normal max unit transmit termination resistor 100 w receiver termination resistor 50 w temperature range C40 125 c power supply v dd 3.13.5v power supply v ss 0v
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 38 lucent technologies inc. lucent technologies inc. timing characteristics 5-8605 (f) figure 11. transmit parallel port timing (backplane -> fpga) table 20 . timing requirements (transmit parallel port timing) symbol parameter min max unit t p clock period 12.86 ns t l clock low time 5.1 7.7 ns t h clock high time 5.1 7.7 ns t su data setup time 3 ns t hd data hold time 0 ns t l t p t h t su t hd first a1 of sts1 #1 sys_clk sys_fp data_tx bus (data bus from fpga to embedded core)
lucent technologies inc. 39 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. timing characteristics (continued) 5-8606 figure 12. transmit transport delay (fpga -> backplane) table 21 . timing requirements (transmit transport delay) symbol parameter min nom max unit t prop number of clocks of delay from parallel bus input to lvds output 4 7 8 sys_clk t prop a1 of sts1 #1 sys_clk sys_fp data_tx bus (parallel data from fpga to embedded core) hdout (lvds data out) first a1 of sts1 #1
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 40 lucent technologies inc. lucent technologies inc. timing characteristics (continued) 5-8607 (f) figure 13. receive parallel port timing ( backplane -> fpga) table 22 . timing requirements (receive parallel port timing) symbol parameter min nom max unit t p clock period 12.86 ns t l clock low time 5.1 6.43 7.7 ns t h clock high time 5.1 6.43 7.7 ns t su data setup time 3 ns t hd data hold time 0 ns t co clock to output time of data, parity, spe, and c1j1 pins 1.3 7 ns t l t p t h t su t hd sys_clk line_fp data_rx bus (from embedded core to fpga) first a1 of sts1 #1 t co parity, spe, c1j1 pins
lucent technologies inc. 41 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. timing characteristics (continued) 5-8608 (f) * data bus refers to 8 bits data, 1 bit parity, 1 bit spe, and 1 bit c1j1. ? channel a or c refers to whether the prot_sw_a or prot_sw_c pins that are activated. for example, if the prot_sw_a pin is activated, the timing diagram for output bus a or c refers to output bus a. figure 14. protection switch timing table 23 . timing requirements (protection switch timing) symbol parameter min nom max unit t tr transport delay from latching of prot_sw_a/c to actual data switch 7 8 9 leading edge sys_clks t hiz transport delay from latching of prot_sw_a/c to actual hi-z 4 5 6 leading edge sys_clks t ch propagation delay from sys_clk to hi-z of output bus 25 leading edge sys_clks t su setup time required from change in prot_sw_a/c to rising sys_clk 3 ns t hd hold time required from rising sys_clk to change in prot_sw_a/c 0 ns sys_clk prot_sw_a ... or prot_sw_c ... ... ... data_rx bus* a or c sys_clk data_rx bus ? a & b or c & d ch a/c ch a/c ch a/c ch a/c ch b/d t tr t su t hd t hiz t ch ch a & b/ ch c & d ch a & b/ ch c & d ch a & b/ ch c & d ch a & b/ ch c & d
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 42 lucent technologies inc. lucent technologies inc. timing characteristics (continued) 5-8609 (f) figure 15. toh input serial port timing (fpga -> backplane) table 24 . timing requirements (toh input serial port timing) symbol parameter min nom max unit t p clock period 12.86 40 ns t hi clock high time 5.1 6.43 7.7 ns t lo clock low time 5.1 6.43 7.7 ns t s data setup time 3 ns t h data hold time 0 ns sys_clk sys_fp ... ... ... ... data_tx bus toh_clk 1044 bytes spe ... ... tx toh_ (parallel bus) toh serial input clk_ena row #1 row #9 36 bytes toh 1044 bytes spe 36 bytes toh guard band (4 toh clk) guard band (4 toh clk) t s t h msbit(7) of b1 byte sts1 #1 bit 6 of b1 byte sts1 #1 t p t hi t lo
lucent technologies inc. 43 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. timing characteristics (continued) 5-8610 (f) note: the total delay from a1 sts1 #1 arriving at lvds input to rx_toh_fp is 56 sys_clks and 6 toh_clks. this will vary by 14 sys_clks, 12 each way for the fifo alignment, and 2 sys_clks due to the variability in the clock recovery of the hsi macro. figure 16. toh output serial port timing (backplane -> fpga) table 25 . timing requirements (toh output serial port timing) symbol parameter min nom max unit t co data clock to out 2 8 ns t trans_sys delay from first a1 lvds serial input to transfer to toh_clk 44 56 68 sys_clks t trans_toh delay from transfer to toh_clk to rx_toh_fp 6 toh_clks rx toh fp hdin toh_clk 1044 bytes spe rx toh (input lvds serial 622m data) toh serial output clk ena row #1 row #9 36 bytes toh 1044 bytes spe 36 bytes toh msbit(7) of a1 byte sts #1 bit 6 of a1 byte sts #1 t trans_sys t trans_toh t co bit 0 of a1 byte sts #1 ... ... ... ... ...
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 44 lucent technologies inc. lucent technologies inc. timing characteristics (continued) 5-8611 (f) note: the cpu interface can be bit stream selected either from device i/o or fpga interface. the timing diagram applies to both interfaces. figure 17. cpu write transaction table 26 . timing requirements (cpu write transaction) symbol parameter min max unit t pulse minimum pulse width for cs_n 5 ns t addr_max maximum time from negative edge of cs_n to addr valid 18ns t dat_max maximum time from negative edge of cs_n to data valid 25ns t rd_wr_max maximum time from negative edge of cs_n to negative edge of rd_wr_n 26ns t write_max maximum time from negative edge of cs_n to contents of internal register latching db[7:0] 60 ns t access_min minimum time between a write cycle (falling edge of cs_n) and any other transaction (read or write at falling edge of cs_n) 60 ns t int_max maximum time from register ff to pad 20 ns t rw_wr_n, addr, db_hold minimum hold time that rd_wr_n, addr and db must be held valid from the negative edge of cs_n 57 ns data valid t access_min t pulse old value new value t write_max t int_max t addr_max t dat_max rd_wr_max cpu_cs_n cpu_rd_wr_n cpu_addr[6:0] cpu_data[7:0] internal register (sys_clk domain) cpu_int_n t rd_wr_n, addr_max, db_hold (cs_n) (rd_wr_n) (addr[6:0]) (db[7:0]) (int_n)
lucent technologies inc. 45 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. timing characteristics (continued) 5-8612 (f) notes: the cpu interface can be bit stream selected either from device i/o or fpga interface. the timing diagram applies to both inter faces. the time delay between the advanced sys_clk and the distributed sys_clk used to sample cs_n is of no consequence. however, the path delay of cs_n from pad to where is it sampled by sys_clk must be minimized. the calculated delays assume a 100 pf loading on the db pins. figure 18. cpu read transaction table 27 . timing requirements (cpu read transaction) symbol parameter min max unit t pulse minimum pulse width for cs_n 5 ns t addr_max maximum time from negative edge of cs_n to addr valid 5 ns t rd_wr_max maximum time from negative edge of cs_n to rd_wr_n falling 5 ns t data_max maximum time from negative edge of cs_n to data valid on db port 56 ns t hiz_max maximum time from rising edge of cs_n to db port going hi-z 12 ns t access_min minimum time between a read cycle (falling edge of cs_n) and any other transaction (read or write at falling edge of cs_n) 60 ns data valid t access_min t pulse t data_max cpu_cs_n cpu_rd_wr_n cpu_addr[6:0] cpu_data[7:0] t hiz_max t addr_max t rd_wr_max (cs_n) (rd_wr_n) (addr[6:0]) (db[7:0])
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 46 lucent technologies inc. lucent technologies inc. input/output buffer measurement conditions note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . figure 19. ac test loads figure 20. output buffer delays figure 21. input buffer delays 5-3234(f) 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k w b. load used to measure rising/falling edges 5-3233.a(f) v dd t phh v dd /2 v ss out[i] pad out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 5-3235(f) 0.0 v 1.5 v t phh t pll pad in[i] in 3.0 v v ss v dd /2 v dd pad in in[i]
lucent technologies inc. 47 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. fpga output buffer characteristics 5-6865(f) figure 22. sinklim (t j = 25 c, v dd = 3.3 v) 5-6867(f) figure 23. slewlim (t j = 25 c, v dd = 3.3 v) 5-6867(f) figure 24. fast (t j = 25 c, v dd = 3.3 v) 5-6866(f) figure 25. sinklim (t j = 125 c, v dd = 3.0 v) 5-6868(f) figure 26. slewlim (t j = 125 c, v dd = 3.0 v) 5-6868(f) figure 27. fast (t j = 125 c, v dd = 3.0 v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 110 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 48 lucent technologies inc. lucent technologies inc. estimating power dissipation this section will be included in a future release of this data sheet. general fpga power estimation parameters can be found in the orca series 3 data sheet.
lucent technologies inc. 49 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. pin information table 28 . fpga common-function pin description * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description dedicated pins v dd 3.3 v power supply. v dd 2 2.5 v power supply gnd ground supply. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as an fpga logic direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i in the master and asynchronous peripheral modes, cclk is an output which strobes configuration data in. in the slave or synchronous peripheral mode, cclk is input synchronous with the data on din or d[7:0]. in microprocessor mode, cclk is used internally and output for daisy-chain operation. done i as an input, a low level on done delays fpga start-up after configuration.* o as an active-high, open-drain output, a high level on this signal indicates that config- uration is complete. done has a permanent pull-up resistor. prgm iprgm is an active-low input that forces the restart of configuration and resets the boundary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during configuration , rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration , rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con- figuration data out. if used in boundary scan, tdo is test data out. special-purpose pins m0, m1, m2 i during powerup and initialization, m0, m1, and m2 are used to select the configura- tion mode with their values latched on the rising edge off init . during configuration, a pull-up is enabled. after configuration, these pins cannot be user-programmable i/os. m3 i during powerup and initialization, m3 is used to select the speed of the internal oscillator during configuration with their values latched on the rising edge of init . when m3 is low, the oscillator frequency is 10 mhz. when m3 is high, the oscillator is 1.25 mhz. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.*
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 50 lucent technologies inc. lucent technologies inc. pin information (continued) table 28. fpga common-function pin description (continued) * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description special-purpose pins (continued) tdi, tck, tms i if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary-scan functions are inhibited once configuration is complete. even if boundary scan is not used, either tck or tms must be held at logic one during configuration. each pin has a pull-up enabled during configuration. i/o after configuration, these pins are user-programmable i/o.* rdy/rclk/ mpi_ale o during configuration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. o during the master parallel configuration mode, rclk is a read output signal to an external memory. this output is not normally used. iin i960 microprocessor mode, this pin acts as the address latch enable (ale) input. i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* hdc o high during configuration (hdc) is output high until configuration is complete. it is used as a control output indicating that configuration is not complete. ldc o low during configuration (ldc ) is output low until configuration is complete. it is used as a control output indicating that configuration is not complete. init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and micropro- cessor configuration modes. the fpga is selected when cs0 is low and cs1 is high. during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral configuration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the microprocessor interface (mpi) data transfer strobe. for powerpc , it is the transfer start (ts). for i960 , it is the address/data strobe (ads ). i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* wr iwr is used in the asynchronous peripheral configuration mode. when the fpga is selected, a low on the write strobe, wr , loads the data on d[7:0] inputs into an inter- nal data buffer. wr and rd should not be used simultaneously. if they are, the write strobe overrides. i/o after configuration, this pin is a user-programmable i/o pin.*
lucent technologies inc. 51 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. pin information (continued) table 28. fpga common-function pin description (continued) symbol i/o description special-purpose pins (continued) mpi_irq o mpi active-low interrupt request output. mpi_bi o powerpc mode mpi burst inhibit output. i/o if the mpi is not in use, this is a user-programmable i/o. mpi_ack oin powerpc mode mpi operation, this is the active-high transfer acknowledge (ta ) output. for i960 mpi operation, it is the active-low ready/record (rdyrcv ) output. if the mpi is not in use, this is a user-programmable i/o. mpi_rw i in powerpc mode mpi operation, this is the active-low write/active-high read control signals. for i960 operation, it is the active-high write/active-low read control signal. i/o if the mpi is not in use, this is a user-programmable i/o. mpi_clk i this is the clock used for the synchronous mpi interface. for powerpc , it is the clk- out signal. for i960 , it is the system clock that is chosen for the i960 external bus interface. i/o if the mpi is not in use, this is a user-programmable i/o. a[4:0] i for powerpc operation, these are the powerpc address inputs. the address bit mapping (in powerpc /fpga notation) is a[31]/a[0], a[30]/a[1], a[29]/a[2], a[28]/ a[3], a[27]/a[4]. note that a[27]/a[4] is the msb of the address. the a[4:2] inputs are not used in i960 mpi mode. i/o if the mpi is not in use, this is a user-programmable i/o. a[1:0]/mpi_be[1:0] ifor i960 operation, mpi_be[1:0] provide the i960 byte enable signals, be[1:0] , that are used as address bits a[1:0] in i960 byte-wide operation. d[7:0] i during peripheral, and slave parallel configuration modes, d[7:0] receive configura- tion data, and each pin has a pull-up enabled. during serial configuration modes, d0 is the din input. d[7:0] are also the data pins for powerpc microprocessor mode and the address/data pins for i960 microprocessor mode. i/o after configuration, the pins are user-programmable i/o pins.* din i during slave serial or master serial configuration modes, din accepts serial configu- ration data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.* dout o during configuration, dout is the serial data output that can drive the din of daisy- chained slave lca devices. data out on dout changes on the falling edge of cclk. i/o after configuration, dout is a user-programmable i/o pin.* * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options.
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 52 lucent technologies inc. lucent technologies inc. pin information (continued) this section describes device i/o signals to/from the embedded core excluding the signals at the cic boundary. table 29. fpsc function pin description symbol i/o description hsi lvds pins sts_ina i lvds input receiver a. sts_inan i lvds input receiver a. sts_inb i lvds input receiver b. sts_inbn i lvds input receiver b. sts_inc i lvds input receiver c. sts_incn i lvds input receiver c. sts_ind i lvds input receiver d. sts_indn i lvds input receiver d. sts_outa o lvds output receiver a. sts_outan o lvds output receiver a. sts_outb o lvds output receiver b. sts_outbn o lvds output receiver b. sts_outc o lvds output receiver c. sts_outcn o lvds output receiver c. sts_outd o lvds output receiver d. sts_outdn o lvds output receiver d. ctap_refa lvds input center tap (rx a) (use 0.01 f to gnd). ctap_refb lvds input center tap (rx b) (use 0.01 f to gnd). ctap_refc lvds input center tap (rx c) (use 0.01 f to gnd). ctap_refd lvds input center tap (rx d) (use 0.01 f to gnd). ref10 i lvds reference voltage: 1.0 v 3%. ref14 i lvds reference voltage: 1.4 v 3%. reshi resistor input (use 100 w 1% to reslo input). reslo resistor input. rext reference resistor for pll (10 k w to ground). pll_v dd a pll analog v dd (3.3 v 5%). pll_v ss a pll analog v ss (gnd). hsi test signals tstmode i enables cdr test mode bypass i enables bypassing of the 622 mhz clock synthesis with tstclk. tstclk i test clock for emulation of 622 mhz clock during pll bypass. mreset i test mode reset. resetrn i resets receiver clock division counter. resettn i resets transmitter clock division counter.
lucent technologies inc. 53 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. hsi test signals (continued) tstshftld i enables the test mode control register for shifting in selected tests by a serial port. ecsel i enables external test control of 622 mhz clock phase selecion. exdnup i direction of phase change. etoggle i moves 622.08 mhz clock selection on phase per positive pulse. loopbken i enables 622 mbits/s loopback mode. tstphase i controls bypass of 16 pll-generated phases with 16 low-speed phases. tstmux[8:0]s o test mode output port. cpu interface pins db<7:0> i/o cpu interface data bus. addr<6:0> i cpu interface address bus. rd_wr_n i cpu interface read/write. cs_n i chip select. int_n o interrupt output. misc system signals rst_n i global reset. external pull-down allows chip to stay in reset state when external driver loses power. sys_clk i system clock (77.76 mhz), 50% duty cycle, also the reference clock of pll. dxp temperature sensing diode (anode +). dxn temperature sensing diode (cathode C). scan and bscan pins* scan_tstmd i scan test mode input. scanen i scan mode enable input. lvds_en i lvds enable used during bscan. during normal operation, lvds_en needs to be pulled high. lvds_en needs to be pulled low for boundary scan. universal bist controller pins sys_dobist i sys_dobist is asserted high to start the bist, should be kept high during the entire bist operation. sys_rssigo o this 32-bit serial out rsb signature consists of the 4-bit fsm state and the bist flag flip-flop states from each sbric_rs element. bc o this flag is asserted to one when bist is complete, is used for polling the end of bist. symbol i/o description * bscan pins-tdi, tdo, tck, tms are on fpga side. pin information (continued) table 29. fpsc function pin description (continued)
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 54 lucent technologies inc. lucent technologies inc. pin information (continued) in table 30, an input refers to a signal flowing into the fgpa logic (out of the embedded core) and an output refers to a signal flowing out of the fpga logic (into the embedded core). table 30. embedded core/fpga interface signal description pin name i/o description data_txa<7:0> o parallel bus of transmitter a. msb is bit 7. data_txa_par o parity for transmitter a. data_txb<7:0> o parallel bus of transmitter b. msb is bit 7. data_txb_par o parity for transmitter b. data_txc<7:0> o parallel bus of transmitter c. msb is bit 7. data_txc_par o parity for transmitter c. data_txd<7:0> o parallel bus of transmitter d. msb is bit 7. data_txd_par o parity for transmitter d. data_rxa<7:0> i parallel bus of receiver a. msb is bit 7. data_rxa_par i parity for parallel bus of receiver a. data_rxa_spe i spe signal for parallel bus of receiver a. data_rxa_c1j1 i c1j1 signal for parallel bus of receiver a. data_rxa_en i enable for parallel bus of receiver a. data_rxb<7:0> i parallel bus of receiver b. msb is bit 7. data_rxb_par i parity for parallel bus of receiver b. data_rxb_spe i spe signal for parallel bus of receiver b. data_rxb_c1j1 i c1j1 signal for parallel bus of receiver b. data_rxb_en i enable for parallel bus of receiver b. data_rxc<7:0> i parallel bus of receiver c. msb is bit 7. data_rxc_par i parity for parallel bus of receiver c. data_rxc_spe i spe signal for parallel bus of receiver c. data_rxc_c1j1 i c1j1 signal for parallel bus of receiver c. data_rxc_en i enable for parallel bus of receiver c. data_rxd<7:0> i parallel bus of receiver d. msb is bit 7. data_rxd_par i parity for parallel bus of receiver d. data_rxd_spe i spe signal for parallel bus of receiver d. data_rxd_c1j1 i c1j1 signal for parallel bus of receiver d. data_rxd_en i enable for parallel bus of receiver d. toh_clk o tx and rx toh serial links clock (25 mhz to 77.76 mhz). toh_txa o toh serial link for transmitter a. toh_txb o toh serial link for transmitter b. toh_txc o toh serial link for transmitter c. toh_txd o toh serial link for transmitter d. tx_toh_ck_en o tx toh serial link clock enable. toh_rxa i toh serial link for receiver a. toh_rxb i toh serial link for receiver b. toh_rxc i toh serial link for receiver c.
lucent technologies inc. 55 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. toh_rxd i toh serial link for receiver d. rx_toh_ck_en i rx toh serial link clock enable. rx_toh_fp i rx toh serial link frame pulse. toh_ck_fp_en i tx toh clock and frame pulse enable. toh_en_a i tx toh enable, soft register control. can be used for channel a, b, c, or d. cpu_data_tx<7:0> o cpu interface data bus. cpu_data_rx<7:0> i cpu interface data bus. cpu_addr<6:0> o cpu interface address bus. cpu_rd_wr_n o cpu interface read/write. cpu_cs_n o chip select. cpu_int_n i interrupt. sys_fp o system frame pulse for transmitter section. line_fp o line frame pulse for receiver section. fpga_sysclk o system clock (77.76 mhz). prot_sw_a o protection switching control signal. prot_sw_c o protection switching control signal. core_ready i flag indicates that the embedded core is out of its reset state. fifosync_fp i the alignment fifo synchronizes and locates the data frames and outputs an optimal frame pulse for the four arriving data streams. cdr_clk_a i 77.76 mhz recovered clock for channel a. cdr_clk_b i 77.76 mhz recovered clock for channel b. cdr_clk_c i 77.76 mhz recovered clock for channel c. cdr_clk_d i 77.76 mhz recovered clock for channel d. rb_mp_sel i bit stream selection for microprocessor interface selection. a 0 indicates the microprocessor interface on the core side is selected. a 1 selects the cpu interface from the fpga side. pin name i/o description pin information (continued) table 30. embedded core/fpga interface signal description (continued)
56 56 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. table 31. embedded core/fpga interface signal locations embedded core/fpga interface site fpga input signal fpga output signal asb1a toh_rxa toh_txa asb1b toh_rxb toh_txb asb1c toh_rxc toh_txc asb1d toh_rxd toh_txd cktoasb1 toh_clk asb2a rx_toh_ck_en asb2b rx_toh_fp asb2c toh_ck_fp_en tx_toh_ck_en asb2d toh_en_a asb3a data_rxa7 asb3b data_rxa6 asb3c data_rxa5 asb3d data_rxa4 asb4a data_rxa3 asb4b data_rxa2 asb4c data_rxa1 asb4d data_rxa0 asb5a data_rxa_par prot_sw_a asb5b data_rxa_spe asb5c data_rxa_c1j1 asb5d data_rxa_en asb6a data_rxtb7 asb6b data_rxb6 asb6c data_rxb5 asb6d data_rxb4 asb7a data_rxb3 asb7b data_rxb2 asb7c data_rxb1 asb7d data_rxb0 asb8a data_rxb_par asb8b data_rxb_spe asb8c data_rxb_c1j1 asb8d data_rxb_en asb9a data_rxc7 asb9b data_rxc6 asb9c data_rxc5 asb9d data_rxc4 asb10a data_rxc3 asb10b data_rxc2 embedded core/fpga interface site fpga input signal fpga output signal asb10c data_rxc1 asb10d data_rxc0 asb11a data_rxc_par prot_sw_c asb11b data_rxc_spe asb11c data_rxc_c1j1 asb11d data_rxc_en asb12a data_rxd7 asb12b data_rxd6 asb12c data_rxd5 asb12d data_rxd4 asb13a data_rxd3 asb13b data_rxd2 asb13c data_rxd1 asb13d data_rxd0 asb14a data_rxd_par line_fp asb14b data_rxd_spe sys_fp asb14c data_rxd_c1j1 asb14d data_rxd_en ckfrasb14 asb15a fifosync_fp data_txa7 asb15b data_txa6 asb15c data_txa5 asb15d data_txa4 asb16a data_txa3 asb16b data_txa2 asb16c data_txa1 asb16d data_txa0 asb17a data_txb7 asb17b data_txb6 asb17c data_txb5 asb17d data_txb4 asb18a data_txb3 asb18b data_txb2 asb18c data_txb1 asb18d data_txb0 asb19a data_txa_par asb19b data_txb_par a s b 1 9 c d ata _ t x c _ pa r a s b 1 9 d d ata _ t x d _ pa r pin information (continued) table 31 lists the physical locations of all signals on the embedded core/fpga interface.
lucent technologies inc. 57 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. embedded core/fpga interface site fpga input signal fpga output signal asb20a data_txc7 asb20b data_txc6 asb20c data_txc5 asb20d data_txc4 asb21a data_txc3 asb21b data_txc2 asb21c data_txc1 asb21d data_txc0 asb22a data_txd7 asb22b data_txd6 asb22c data_txd5 asb22d data_txd4 asb23a data_txd3 asb23b data_txd2 asb23c data_txd1 asb23d data_txd0 asb24a cpu_data_rx7 cpu_data_tx7 asb24b cpu_data_rx6 cpu_data_tx6 asb24c cpu_data_rx5 cpu_data_tx5 embedded core/fpga interface site fpga input signal fpga output signal asb24d cpu_data_rx4 cpu_data_tx4 asb25a cpu_data_rx3 cpu_data_tx3 asb25b cpu_data_rx2 cpu_data_tx2 asb25c cpu_data_rx1 cpu_data_tx1 asb25d cpu_data_rx0 cpu_data_tx0 asb26a cpu_int_n cpu_addr6 asb26b cpu_addr5 asb26c cpu_addr4 asb26d core_ready cpu_addr3 asb27a cpu_addr2 asb27b cpu_addr1 asb27c cpu_addr0 asb27d cpu_rd_wr_n asb28a cdr_clk_a cpu_cs_n asb28b cdr_clk_b asb28c cdr_clk_c asb28d cdr_clk_d bmlkcntl fpga_sysclk pin information (continued) table 31. embedded core/fpga interface signal locations (continued)
58 58 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin information (continued) the ort4622 is pin compatible with a series 3 or3l125b device in the same package in terms of v dd , v ss , configuration, and special function pins. the uses and characteristics of the fpga user i/o pins in the embed- ded core area of the device have changed to support the ort4622 functionality. additionally, the lower-left pro- grammable clock manager (pcm) clock input pin (seckll) has been relocated. table 32. 432-pin ebga pinout pin ort4622 pad function e4 prd_cfgn rd_cfg d3 pr1d i/o d2 pr1c i/o d1 pr1b i/o f4 pr1a i/o e3 pr2d i/o e2 pr2c i/o e1 pr2b i/o f3 pr2a i/o f2 pr3d i/o f1 pr3c i/o h4 pr3b i/o g3 pr3a i/o-wr g2 pr4d i/o g1 pr4c i/o j4 pr4b i/o h3 v dd 2v dd 2 h2 pr5a i/o j3 pr6c i/o k4 pr6a i/o j2 pr7a i/o-rd /mpi_strb j1 pr8d i/o k3 pr8c i/o k2 pr8b i/o k1 pr8a i/o l3 pr9d i/o m4 pr9c i/o l2 pr9b i/o l1 pr9a i/o-cs0 m3 pr10d i/o n4 pr10a i/o m2 pr11d i/o n3 pr11a i/o-cs1 n2 pr12d i/o p4 pr12c i/o n1 pr12a i/o p3 pr13d i/o p2 pr13c i/o pin ort4622 pad function p1 v dd 2v dd 2 r3 pr14d i/o r2 pr14c i/o r1 pr14b i/o t2 peckr i/o-eckr t4 pr15d i/o t3 pr15c i/o u1 pr15b i/o u2 pr15a i/o u3 pr16d i/o v1 pr16b i/o v2 pr16a i/o v3 pr17d i/o w1 pr17a i/o-m3 v4 pr18d i/o w2 pr18b i/o w3 pr18a i/o y2 pr19d w4 pr19a m2 y3 pr20d aa1 pr20c aa2 pr20b y4 pr20a aa3 v dd 2v dd 2 ab1 pr21c ab2 pr21b ab3 pr21a ac1 pr22d m1 ac2 pr23d ab4 pr23b ac3 pr23a ad2 pr24a ad3 pr25c ac4 pr25b ae1 pr25a db3 (core) ae2 pr26d db2 (core) ae3 pr26c db1 (core) ad4 pr26b db0 (core)
lucent technologies inc. 59 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. pin information (continued) table 32. 432-pin ebga pinout (continued) pin ort4622 pad function af1 pr26a db7 (core) af2 pr27d db6 (core) af3 pr27c db5 (core) ag1 pr27b db4 (core) ag2 v dd 2v dd 2 ag3 pr28d int_n (core) af4 pr28c ah1 pr28b rst_n ah2 pr28a m0 ah3 pprgmn prgm ag4 presetn reset ah5 pdone done aj4 pb28d rd_wr_n (core) ak4 pb28c cs_n (core) al4 pb28b addr0 (core) ah6 pb28a addr1 (core) aj5 pb27d addr2 (core) ak5 pb27c addr3 (core) al5 pb27b addr4 (core) aj6 pb27a addr5 (core) ak6 pb26d addr6 (core) al6 pb26c tstmux0s (core) ah8 pb26b tstmux1s (core) aj7 pb26a tstmux2s (core) ak7 pb25d tstmux4s (core) al7 pb25c tstmux7s (core) ah9 pb25b tstmux3s (core) aj8 v dd 2v dd 2 ak8 pb24d tstmux6s (core) aj9 pb24c tstmux5s (core) ah10 pb24b tstmux8s (core) ak9 pb24a init al9 pb23d tstphase (core) aj10 pb23c loopbken (core) ak10 pb23a exdnup (core) al10 pb22a ecsel (core) aj11 pb21d etoggle (core) ah12 pb21a resettn (core) ak11 pb20d mreset (core) pin ort4622 pad function al11 pb20a ldc aj12 pb19d tstshftld (core) ah13 pb19b resetrn (core) ak12 pb19a tstclk (core) aj13 pb18d bypass (core) ak13 pb18b tstmode (core) ah14 pb18a hdc al13 pb17d aj14 pb17b ak14 pb17a sys_clk (core) al14 pb16d aj15 v dd 2v dd 2 ak15 pb15d sts_outd (core) al15 pb15c sts_outdn (core) ak16 pb15b ah16 peckb sts_outc (core) aj16 pb14d sts_outcn (core) al17 pb14c reslo (core) ak17 pb14b reshi (core) aj17 pb14a al18 pb13d ref14 (core) ak18 pb13b ref10 (core) aj18 pb13a rext al19 pb12d pll_v ss a ah18 pb12a pll_v dd a ak19 pb11d sts_outb (core) aj19 pb11b sts_outbn (core) ak20 pb11a ah19 pb10d sts_outa (core) aj20 pb10b sts_outan (core) al21 v dd 2v dd 2 ak21 pb9d ctap_refd (core) ah20 pb9a sts_ind (core) aj21 pb8d sts_indn (core) al22 pb8a sts_inc (core) ak22 pb7d sts_incn (core) aj22 pb7a ctap_refc (core) al23 pb6d sts_inb (core) ak23 pb6a sts_inbn (core)
60 60 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin information (continued) table 32. 432-pin ebga pinout (continued) pin ort4622 pad function ah22 pb5d ctap_refb (core) aj23 pb5c sts_ina (core) ak24 pb5b sts_inan (core) aj24 pb5a ctap_refa (core) ah23 pb4d al25 pb4c ak25 pb4b aj25 pb4a lvds_en (core) ah24 pb3d scan_tstmd (core) al26 pb3c scanen (core) ak26 pb3b dxp (core) aj26 pb3a dxn (core) al27 v dd 2v dd 2 ak27 pb2c sys_dobist (core) aj27 pb2b sys_rssigo (core) ah26 pb2a bc (core) al28 pb1d ak28 pb1c aj28 pb1b ah27 pb1a ag28 pcclk cclk ah29 pl28a ah30 pl28b ah31 pl28c af28 pl28d ag29 pl27a ag30 pl27b ag31 pl27c af29 pl27d af30 pl26a af31 pl26b ad28 pl26c ae29 v dd 2v dd 2 ae30 pl25a ae31 pl25b ac28 pl25c ad29 pl24a ad30 pl24d ac29 pl23d ab28 pl22c pin ort4622 pad function ac30 pl22d ac31 pl21a ab29 pl21b ab30 pl21c ab31 pl21d aa29 pl20a y28 pl20b aa30 pl20c aa31 pl20d y29 pl19a mpi_irq w28 pl19d y30 pl18a i/o-seckll w29 pl18c i/o w30 pl18d i/o v28 pl17a i/o-mpi_bi w31 pl17c i/o v29 pl17d i/o v30 pl16a i/o v31 pl16c i/o u29 pl16d i/o u30 pl15a i/o-mpi_rw u31 pl15b i/o t30 v dd 2v dd 2 t28 pl15d i/o t29 pl14a i/o-mpi_clk r31 pl14b i/o r30 pl14c i/o r29 peckl i/o-eckl p31 pl13a i/o p30 pl13d i/o p29 pl12a i/o n31 pl12c i/o p28 pl12d i/o n30 pl11a i/o-a4 n29 pl11c i/o m30 pl11d i/o n28 pl10a i/o m29 pl10c i/o l31 v dd 2v dd 2 l30 pl9a i/o-a3
lucent technologies inc. 61 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. pin information (continued) table 32. 432-pin ebga pinout (continued) pin ort4622 pad function m28 pl9b i/o l29 pl9c i/o k31 pl9d i/o k30 pl8a i/o-a2 k29 pl8b i/o j31 pl8c i/o j30 pl8d i/o k28 pl7d i/o-a1/mpi_be1 j29 pl6b i/o h30 pl6c i/o h29 pl6d i/o j28 pl5d i/o g31 pl4b i/o g30 pl4c i/o g29 v dd 2v dd 2 h28 pl3a i/o f31 pl3b i/o f30 pl3c i/o f29 pl3d i/o e31 pl2a i/o e30 pl2b i/o e29 pl2c i/o f28 pl2d i/o-a0/mpi_be0 d31 pl1a i/o d30 pl1b i/o d29 pl1c i/o e28 pl1d i/o d27 prd_data rd_data/tdo c28 pt1a i/o-tck b28 pt1b i/o a28 pt1c i/o d26 pt1d i/o c27 pt2a i/o b27 pt2b i/o a27 pt2c i/o c26 pt2d i/o b26 pt3a i/o a26 pt3b i/o d24 pt3c i/o pin ort4622 pad function c25 pt3d i/o b25 pt4a i/o-tms a25 pt4b i/o d23 pt4c i/o c24 pt4d i/o b24 v dd 2v dd 2 c23 pt5b i/o d22 pt5c i/o b23 pt5d i/o a23 pt6a i/o-tdi c22 pt6d i/o b22 pt7a i/o a22 pt7d i/o c21 pt8a i/o d20 pt8d i/o b21 pt9a i/o a21 pt9d i/o c20 pt10a i/o-dout d19 pt10d i/o b20 pt11a i/o c19 pt11c i/o b19 pt11d i/o d18 pt12a i/o-d0/din a19 pt12c i/o c18 pt12d i/o b18 pt13a i/o a18 pt13c i/o c17 pt13d i/o-d1 b17 pt14a i/o-d2 a17 v dd 2v dd 2 b16 pt14c i/o d16 pt14d i/o c16 pt15a i/o-d3 a15 pt15b i/o b15 pt15c i/o c15 peckt i/o-eckt a14 pt16a i/o-d4 b14 pt16b i/o c14 pt16d i/o
62 62 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin information (continued) table 32. 432-pin ebga pinout (continued) pin ort4622 pad function a13 pt17a i/o d14 pt17b i/o b13 pt17d i/o c13 pt18a i/o-d5 b12 pt18b i/o d13 v dd 2v dd 2 c12 pt19a i/o a11 pt19d i/o b11 pt20a i/o d12 pt20d i/o-d6 c11 pt21a i/o a10 pt21d i/o b10 pt22d i/o c10 pt23b i/o a9 pt23c i/o b9 v dd 2v dd 2 d10 pt24a i/o c9 pt24b i/o b8 pt24c i/o c8 pt24d i/o-d7 d9 pt25a i/o a7 pt25b i/o b7 pt25c i/o c7 pt25d i/o d8 pt26a i/o a6 pt26b i/o b6 pt26c i/o c6 pt26d i/o a5 pt27a i/o-rdy/rclk b5 pt27b i/o c5 pt27c i/o d6 pt27d i/o a4 pt28a i/o b4 pt28b i/o c4 pt28c i/o d5 pt28d i/o-seckur a12 v ss v ss a16 v ss v ss a2 v ss v ss a20 v ss v ss a24 v ss v ss a29 v ss v ss pin ort4622 pad function a3 v ss v ss a30 v ss v ss a8 v ss v ss ad1 v ss v ss ad31 v ss v ss aj1 v ss v ss aj2 v ss v ss aj30 v ss v ss aj31 v ss v ss ak1 v ss v ss ak29 v ss v ss ak3 v ss v ss ak31 v ss v ss al12 v ss v ss al16 v ss v ss al2 v ss v ss al20 v ss v ss al24 v ss v ss al29 v ss v ss al3 v ss v ss al30 v ss v ss al8 v ss v ss b1 v ss v ss b29 v ss v ss b3 v ss v ss b31 v ss v ss c1 v ss v ss c2 v ss v ss c30 v ss v ss c31 v ss v ss h1 v ss v ss h31 v ss v ss m1 v ss v ss m31 v ss v ss t1 v ss v ss t31 v ss v ss y1 v ss v ss y31 v ss v ss a1 v dd v dd a31 v dd v dd aa28 v dd v dd aa4 v dd v dd
lucent technologies inc. 63 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. pin information (continued) table 32. 432-pin ebga pinout (continued) pin ort4622 pad function ae28 v dd v dd ae4 v dd v dd ah11 v dd v dd ah15 v dd v dd ah17 v dd v dd ah21 v dd v dd ah25 v dd v dd ah28 v dd v dd ah4 v dd v dd ah7 v dd v dd aj29 v dd v dd aj3 v dd v dd ak2 v dd v dd ak30 v dd v dd al1 v dd v dd al31 v dd v dd b2 v dd v dd b30 v dd v dd pin ort4622 pad function c29 v dd v dd c3 v dd v dd d11 v dd v dd d15 v dd v dd d17 v dd v dd d21 v dd v dd d25 v dd v dd d28 v dd v dd d4 v dd v dd d7 v dd v dd g28 v dd v dd g4 v dd v dd l28 v dd v dd l4 v dd v dd r28 v dd v dd r4 v dd v dd u28 v dd v dd u4 v dd v dd
64 64 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin information (continued) table 33. 680-pin pbgam pinout pin ort4622 pad function d1 pl1d i/o e2 e1 f4 pl1c i/o f3 pl1b i/o f2 pl1a i/o f1 pl2d i/o-a0 g5 pl2c i/o g4 pl2b i/o g2 pl2a i/o g1 pl3d i/o h5 pl3c i/o h4 pl3b i/o h2 pl3a i/o h1 pl4c i/o j5 pl4b i/o j4 pl4a i/o j3 pl5d i/o j2 pl5c i/o j1 pl5b i/o k5 pl5a i/o k4 pl6d i/o k3 pl6c i/o k2 pl6b i/o k1 pl6a i/o l5 pl7d i/o-a1 l4 pl7c i/o l2 pl7b i/o l1 pl7a i/o m5 pl8d i/o m4 pl8c i/o m2 pl8b i/o m1 pl8a i/o-a2 n5 pl9d i/o n4 pl9c i/o n3 pl9b i/o n2 pl9a i/o-a3 n1 pl10c i/o p5 pl10b i/o p4 pl10a i/o pin ort4622 pad function p3 pl11d i/o p2 pl11c i/o p1 pl11b i/o r5 pl11a i/o-a4 r4 pl12d i/o-a5 r2 pl12c i/o r1 pl12b i/o t5 pl13d i/o t4 pl13c i/o t2 pl13b i/o t1 pl13a i/o u5 peckl i/o-eckl u4 u3 pl14c i/o u2 pl14b i/o u1 pl14a i/o v1 pl15d i/o v2 pl15b i/o v3 pl15a i/o v4 pl16d i/o v5 pl16c i/o w1 pl16b i/o w2 pl16a i/o w4 pl17d i/o w5 pl17c i/o y1 pl17b i/o y2 pl17a i/o y4 pl18d i/o y5 pl18c i/o aa1 pl18b i/o aa2 pl18a i/o-seckll aa3 pl19d aa4 pl19c aa5 pl19b ab1 pl19a mpi_irq ab2 pl20d ab3 pl20c ab4 pl20a ab5 pl21d ac1 pl21c
lucent technologies inc. 65 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. pin ort4622 pad function ac2 pl21b ac4 pl21a ac5 pl22d ad1 pl22c ad2 pl22b ad4 pl22a ad5 pl23d ae1 pl23c ae2 pl23b ae3 pl23a ae4 pl24d ae5 pl24c af1 pl24b af2 pl24a af3 pl25d af4 pl25c af5 pl25b ag1 pl25a ag2 pl26c ag4 pl26b ag5 pl26a ah1 pl27d ah2 pl27c ah4 pl27b ah5 pl27a aj1 aj2 aj3 pl28d aj4 pl28c ak1 pl28b ak2 pl28a al1 pcclk cclk ap4 pb1a an5 pb1b ap5 al6 am6 pb1c an6 pb1d ap6 pb2a bc ak7 pb2b sys_rssigo al7 pb2c sys_dobist pin ort4622 pad function an7 pb3a dxn (core) ap7 pb3b dxp (core) ak8 pb3c scanen (core) al8 pb3d scan_tstmd (core) an8 pb4a lvds_en (core) ap8 pb4b ak9 pb4c al9 pb4d am9 pb5a ctap_refa (core) an9 pb5b sts_inan (core) ap9 pb5c sts_ina (core) ak10 pb5d ctap_refb (core) al10 pb6a sts_inbn (core) am10 pb6b sts_inb (core) an10 pb6c ap10 pb6d ak11 pb7a ctap_refc (core) al11 pb7b an11 pb7c ap11 pb7d ak12 pb8a sts_incn (core) al12 pb8b sts_inc (core) an12 pb8c sts_indn (core) ap12 pb8d sts_ind (core) ak13 pb9a al13 pb9b am13 pb9c an13 pb9d ctap_refd (core) ap13 pb10b ak14 pb10c sts_outan (core) al14 pb10d sts_outa (core) am14 pb11a an14 pb11b sts_outbn (core) ap14 pb11c sts_outb (core) ak15 pb11d al15 pb12a pll_vdda (core) an15 pb12b ap15 pb12c ak16 pb12d pll_vssa (core) pin information (continued) table 33. 680-pin pbgam pinout (continued)
66 66 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin ort4622 pad function al16 pb13a rext (core) an16 pb13b ref10 (core) ap16 pb13c ak17 pb13d ref14 (core) al17 am17 pb14b reshi (core) an17 ap17 pb14c reslo (core) ap18 pb14d sts_outcn (core) an18 peckb sts_outc (core) am18 pb15b al18 pb15c sts_outdn (core) ak18 pb15d sts_outd (core) ap19 pb16b an19 pb16c al19 pb16d ak19 pb17a sys_clk ap20 pb17b an20 pb17c al20 pb17d ak20 pb18a hdc ap21 pb18b tstmode an21 pb18c am21 pb18d bypass al21 pb19a tstclk ak21 pb19b resetrn ap22 pb19c tstshftld an22 pb20a ldc am22 pb20b al22 pb20c ak22 pb20d mreset (core) ap23 pb21a resettn (core) an23 pb21b al23 pb21c ak23 pb21d etoggle (core) ap24 pb22a ecsel (core) an24 pb22b al24 pb22c pin ort4622 pad function ak24 pb22d ap25 pb23a exdnup (core) an25 pb23b am25 pb23c loopbken (core) al25 pb23d tstphase (core) ak25 pb24a init ap26 pb24b tstmux8s (core) an26 pb24c tstmux5s (core) am26 pb24d tstmux6s (core) al26 pb25b tstmux3s (core) ak26 pb25c tstmux7s (core) ap27 pb25d tstmux4s (core) an27 pb26a tstmux2s (core) al27 pb26b tstmux1s (core) ak27 pb26c tstmux0s (core) ap28 pb26d addr6 (core) an28 pb27a addr5 (core) al28 pb27b addr4 (core) ak28 pb27c addr3 (core) ap29 pb27d addr2 (core) an29 pb28a addr1 (core) am29 pb28b addr0 (core) al29 ap30 pb28c cs_n (core) an30 pb28d rd_wr_n (core) ap31 pdone done al34 presetn reset ak33 pprgmn prgm ak34 pr28a m0 aj31 pr28b rst_n aj32 pr28c aj33 pr28d int_n aj34 pr27b db4 (core) ah30 pr27c db5 (core) ah31 pr27d db6 (core) ah33 pr26a db7 (core) ah34 pr26b db0 (core) ag30 pr26c db1 (core) pin information (continued) table 33. 680-pin pbgam pinout (continued)
lucent technologies inc. 67 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. pin information (continued) table 33. 680-pin pbgam pinout (continued) pin ort4622 pad function ag31 pr26d db2 (core) ag33 pr25a db3 (core) ag34 pr25b af30 pr25c af31 pr25d af32 pr24a af33 pr24b af34 pr24c ae30 pr24d ae31 pr23a ae32 pr23b ae33 pr23c ae34 pr23d ad30 pr22a ad31 pr22b ad33 pr22c ad34 pr22d m1 ac30 pr21a ac31 pr21b ac33 pr21c ac34 pr20a ab30 pr20b ab31 pr20c ab32 pr20d ab33 pr19a m2 ab34 pr19b aa30 pr19c aa31 pr19d aa32 pr18a i/o aa33 pr18b i/o aa34 pr18c i/o y30 pr18d i/o y31 pr17a i/o-m3 y33 pr17b i/o y34 pr17c i/o w30 pr17d i/o w31 pr16a i/o w33 pr16b i/o w34 pr16c i/o v30 pr15a i/o v31 v32 pr15b i/o pin ort4622 pad function v33 pr15c i/o v34 pr15d i/o u34 peckr i/o-eckr u33 pr14b i/o u32 pr14c i/o u31 pr14d i/o u30 pr13b i/o t34 pr13c i/o t33 pr13d i/o t31 pr12a i/o t30 pr12b i/o r34 pr12c i/o r33 pr12d i/o r31 pr11a i/o-cs1 r30 pr11b i/o p34 pr11c i/o p33 pr11d i/o p32 pr10a i/o p31 pr10b i/o p30 pr10c i/o n34 pr9a i/o-cs0 n33 pr9b i/o n32 pr9c i/o n31 pr9d i/o n30 pr8a i/o m34 pr8b i/o m33 pr8c i/o m31 pr8d i/o m30 pr7a i/o-rd l34 pr7b i/o l33 pr7c i/o l31 pr7d i/o l30 pr6a i/o k34 pr6b i/o k33 pr6c i/o k32 pr6d i/o k31 pr5a i/o k30 pr5b i/o j34 pr5c i/o j33 pr5d i/o j32 pr4b i/o j31 pr4c i/o
68 68 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin information (continued) table 33. 680-pin pbgam pinout (continued) pin ort4622 pad function j30 pr4d i/o h34 pr3a i/o-wr h33 pr3b i/o h31 pr3c i/o h30 pr3d i/o g34 pr2a i/o g33 pr2b i/o g31 pr2c i/o g30 pr2d i/o f34 pr1a i/o f33 f32 pr1b i/o f31 pr1c i/o e34 e33 pr1d i/o d34 prd_cfgn rd_cfg a31 pt28d i/o-seckur b30 a30 pt28c i/o d29 c29 pt28b i/o b29 pt28a i/o a29 pt27d i/o e28 pt27c i/o d28 pt27b i/o b28 pt27a i/o-rdy/rclk a28 pt26d i/o e27 pt26c i/o d27 pt26b i/o b27 pt26a i/o a27 pt25d i/o e26 pt25c i/o d26 pt25b i/o c26 pt25a i/o b26 pt24d i/o-d7 a26 pt24c i/o e25 pt24b i/o d25 pt24a i/o c25 pt23c i/o b25 pt23b i/o a25 pt23a i/o e24 pt22d i/o pin ort4622 pad function d24 pt22c i/o b24 pt22b i/o a24 pt22a i/o e23 pt21d i/o d23 pt21c i/o b23 pt21b i/o a23 pt21a i/o e22 pt20d i/o-d6 d22 pt20c i/o c22 pt20b i/o b22 pt20a i/o a22 pt19d i/o e21 pt19c i/o d21 pt19b i/o c21 pt19a i/o b21 pt18c i/o a21 pt18b i/o e20 pt18a i/o-d5 d20 pt17d i/o b20 pt17c i/o a20 pt17b i/o e19 pt17a i/o d19 pt16d i/o b19 pt16c i/o a19 pt16b i/o e18 pt16a i/o-d4 d18 peckt i/o-eckt c18 pt15b i/o b18 a18 pt15a i/o-d3 a17 pt14d i/o b17 pt14c i/o c17 pt14a i/o-d2 d17 pt13d i/o-d1 e17 pt13c i/o a16 pt13b i/o b16 pt13a i/o d16 pt12d i/o e16 pt12c i/o a15 pt12b i/o b15 pt12a i/o-d0/din d15 pt11d i/o
lucent technologies inc. 69 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. pin ort4622 pad function e15 pt11c i/o a14 pt11b i/o b14 pt11a i/o c14 pt10d i/o d14 pt10c i/o e14 pt10b i/o a13 pt10a i/o-dout b13 pt9c i/o c13 pt9b i/o d13 pt9a i/o e13 pt8d i/o a12 pt8c i/o b12 pt8b i/o d12 pt8a i/o e12 pt7d i/o a11 pt7c i/o b11 pt7b i/o d11 pt7a i/o e11 pt6d i/o a10 pt6c i/o b10 pt6b i/o c10 pt6a i/o-tdi d10 pt5d i/o e10 pt5c i/o a9 pt5b i/o b9 pt4d i/o c9 pt4c i/o d9 pt4b i/o e9 pt4a i/o-tms a8 pt3d i/o b8 pt3c i/o d8 pt3b i/o e8 pt3a i/o a7 pt2d i/o b7 pt2c i/o d7 pt2b i/o e7 pt2a i/o a6 pt1d i/o b6 c6 pt1c i/o d6 pt1b i/o a5 b5 pt1a i/o-tck pin ort4622 pad function a4 prd_data rd_data/tdo a1 v ss v ss a2 v ss v ss a33 v ss v ss a34 v ss v ss b1 v ss v ss b2 v ss v ss b33 v ss v ss b34 v ss v ss c3 v ss v ss c8 v ss v ss c12 v ss v ss c16 v ss v ss c19 v ss v ss c23 v ss v ss c27 v ss v ss c32 v ss v ss d4 v ss v ss d31 v ss v ss h3 v ss v ss h32 v ss v ss m3 v ss v ss m32 v ss v ss n13 v ss v ss n14 v ss v ss n15 v ss v ss n20 v ss v ss n21 v ss v ss n22 v ss v ss p13 v ss v ss p14 v ss v ss p15 v ss v ss p20 v ss v ss p21 v ss v ss p22 v ss v ss r13 v ss v ss r14 v ss v ss r15 v ss v ss r20 v ss v ss r21 v ss v ss r22 v ss v ss t3 v ss v ss t16 v ss v ss pin information (continued) table 33. 680-pin pbgam pinout (continued)
70 70 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin information (continued) table 33. 680-pin pbgam pinout (continued) pin ort4622 pad function t17 v ss v ss t18 v ss v ss t19 v ss v ss t32 v ss v ss u16 v ss v ss u17 v ss v ss u18 v ss v ss u19 v ss v ss v16 v ss v ss v17 v ss v ss v18 v ss v ss v19 v ss v ss w3 v ss v ss w16 v ss v ss w17 v ss v ss w18 v ss v ss w19 v ss v ss w32 v ss v ss y13 v ss v ss y14 v ss v ss y15 v ss v ss y20 v ss v ss y21 v ss v ss y22 v ss v ss aa13 v ss v ss aa14 v ss v ss aa15 v ss v ss aa20 v ss v ss aa21 v ss v ss aa22 v ss v ss ab13 v ss v ss ab14 v ss v ss ab15 v ss v ss ab20 v ss v ss ab21 v ss v ss ab22 v ss v ss ac3 v ss v ss ac32 v ss v ss ag3 v ss v ss ag32 v ss v ss al4 v ss v ss al31 v ss v ss pin ort4622 pad function am3 v ss v ss am8 v ss v ss am12 v ss v ss am16 v ss v ss am19 v ss v ss am23 v ss v ss am27 v ss v ss am32 v ss v ss an1 v ss v ss an2 v ss v ss an33 v ss v ss an34 v ss v ss ap1 v ss v ss ap2 v ss v ss ap33 v ss v ss ap34 v ss v ss c5 v dd 2v dd 2 c30 v dd 2v dd 2 d5 v dd 2v dd 2 d30 v dd 2v dd 2 e3 v dd 2v dd 2 e4 v dd 2v dd 2 e5 v dd 2v dd 2 e6 v dd 2v dd 2 e29 v dd 2v dd 2 e30 v dd 2v dd 2 e31 v dd 2v dd 2 e32 v dd 2v dd 2 f5 v dd 2v dd 2 f30 v dd 2v dd 2 n16 v dd 2v dd 2 n17 v dd 2v dd 2 n18 v dd 2v dd 2 n19 v dd 2v dd 2 p16 v dd 2v dd 2 p17 v dd 2v dd 2 p18 v dd 2v dd 2 p19 v dd 2v dd 2 r16 v dd 2v dd 2 r17 v dd 2v dd 2 r18 v dd 2v dd 2 r19 v dd 2v dd 2
lucent technologies inc. 71 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s back p lane transceiver lucent technologies inc. pin information (continued) table 33. 680-pin pbgam pinout (continued) pin ort4622 pad function t13 v dd 2v dd 2 t14 v dd 2v dd 2 t15 v dd 2v dd 2 t20 v dd 2v dd 2 t21 v dd 2v dd 2 t22 v dd 2v dd 2 u13 v dd 2v dd 2 u14 v dd 2v dd 2 u15 v dd 2v dd 2 u20 v dd 2v dd 2 u21 v dd 2v dd 2 u22 v dd 2v dd 2 v13 v dd 2v dd 2 v14 v dd 2v dd 2 v15 v dd 2v dd 2 v20 v dd 2v dd 2 v21 v dd 2v dd 2 v22 v dd 2v dd 2 w13 v dd 2v dd 2 w14 v dd 2v dd 2 w15 v dd 2v dd 2 w20 v dd 2v dd 2 w21 v dd 2v dd 2 w22 v dd 2v dd 2 y16 v dd 2v dd 2 y17 v dd 2v dd 2 y18 v dd 2v dd 2 y19 v dd 2v dd 2 aa16 v dd 2v dd 2 aa17 v dd 2v dd 2 aa18 v dd 2v dd 2 aa19 v dd 2v dd 2 ab16 v dd 2v dd 2 ab17 v dd 2v dd 2 ab18 v dd 2v dd 2 ab19 v dd 2v dd 2 aj5 v dd 2v dd 2 aj30 v dd 2v dd 2 ak3 v dd 2v dd 2 ak4 v dd 2v dd 2 ak5 v dd 2v dd 2 pin ort4622 pad function ak6 v dd 2v dd 2 ak29 v dd 2v dd 2 ak30 v dd 2v dd 2 ak31 v dd 2v dd 2 ak32 v dd 2v dd 2 al5 v dd 2v dd 2 al30 v dd 2v dd 2 am5 v dd 2v dd 2 am30 v dd 2v dd 2 a3 v dd v dd a32 v dd v dd b3 v dd v dd b4 v dd v dd b31 v dd v dd b32 v dd v dd c1 v dd v dd c2 v dd v dd c4 v dd v dd c7 v dd v dd c11 v dd v dd c15 v dd v dd c20 v dd v dd c24 v dd v dd c28 v dd v dd c31 v dd v dd c33 v dd v dd c34 v dd v dd d2 v dd v dd d3 v dd v dd d32 v dd v dd d33 v dd v dd g3 v dd v dd g32 v dd v dd l3 v dd v dd l32 v dd v dd r3 v dd v dd r32 v dd v dd y3 v dd v dd y32 v dd v dd ad3 v dd v dd ad32 v dd v dd
72 72 lucent technologies inc. orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. pin ort4622 pad function ah3 v dd v dd ah32 v dd v dd al2 v dd v dd al3 v dd v dd al32 v dd v dd al33 v dd v dd am1 v dd v dd am2 v dd v dd am4 v dd v dd am7 v dd v dd am11 v dd v dd am15 v dd v dd pin ort4622 pad function am20 v dd v dd am24 v dd v dd am28 v dd v dd am31 v dd v dd am33 v dd v dd am34 v dd v dd an3 v dd v dd an4 v dd v dd an31 v dd v dd an32 v dd v dd ap3 v dd v dd ap32 v dd v dd pin information (continued) table 33. 680-pin pbgam pinout (continued)
lucent technologies inc. 73 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. package thermal characteristics summary there are three thermal parameters that are in com- mon use: q ja , y jc, and q jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. q ja this is the thermal resistance from junction to ambient (a.k.a. theta-ja, r-theta, etc.). where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, q ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that q ja is expressed in units of c/watt. y jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the q ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. y jc is also expressed in units of c/watt. q jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates q jc from y jc. q jc is a true thermal resistance and is expressed in units of c/watt. q jb this is the thermal resistance from junction to board (a.k.a. q jl ). it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that q jb is expressed in units of c/watt, and that this parameter and the way it is mea- sured are still in jedec committee. fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpga can be found. this is needed to determine if speed der- ating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the max- imum junction temperature is approximated by: t jmax = t amax + (q ? q ja ) ta b l e 3 4 lists the thermal characteristics for all pack- ages used with the orca ort4622 series of fpgas. q ja t j t a C q ------------------- - = y jc t j t c C q -------------------- = q jc t j t c C q -------------------- = q jb t j t b C q ------------------- - =
74 lucent technologies inc. orca ort4622 fpsc advanced data sheet four-channel x 622 mbits/s backplane transceiver november 1999 lucent technologies inc. package thermal characteristics table 34 . orca ort4622 plastic package thermal guidelines package q ja ( c/w) t amb = 70 c max t j = 125 c max 0 fpm (w) 0 fpm 200 fpm 500 fpm 432-pin ebga 11 8.5 5 5 680-pin pbgam 14.5 tbd tbd 3.8 package coplanarity the coplanarity limits of the orca series 3/3+ pack- ages are as follows: n ebga: 8.0 mils n pbgam: 8.0 mils package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 35 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capaci- tance of the lead to the nearest neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. resistance values are in m w. the parasitic values in table 35 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors.
lucent technologies inc. 75 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. package parasitics (continued) table 35 . orca ort4622 package parasitics 5-3862(c)r2 figure 28. package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 432-pin ebga 4 1.5 500 1.0 1.0 0.3 35.5 0.51 680-pin pbgam 3.8 1.3 250 1.0 1.0 0.3 2.85 0.51 pad n l sw r w circuit board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 76 lucent technologies inc. lucent technologies inc. package outline diagrams terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
lucent technologies inc. 77 advance data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. package outline diagrams (continued) 432-pin ebga dimensions are in millimeters. 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 24 22 23 25 7 20 31 29 15 21 18 327 11 17 4 6 810121416 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner
orca ort4622 fpsc advance data sheet four-channel x 622 mbits/s backplane transceiver november 1999 78 lucent technologies inc. lucent technologies inc. package outline diagrams (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10121416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 C 0.00 35.00 30.00 + 0.70 C 0.00 identifier zone 2.51 max 0.61 0.08
lucent technologies inc. 79 advanced data sheet orca ort4622 fpsc november 1999 four-channel x 622 mbits/s backplane transceiver lucent technologies inc. ordering information 5-6435 (f).i device type package type ort4622 -8 bc number of pins temperature range 432 fpga speed grade table 36. voltage options table 37. temperature options table 38. package type options table 39 . orca series 3+ package matrix key: c = commercial, i = industrial. device voltage ort4622 2.5 v/3.3 v symbol description temperature (blank) commercial 0 c to 70 c i industrial C 40 c to +85 c symbol description bc enhanced ball grid array (ebga) bm plastic ball grid array, multilayer device package 432-pin ebga 680-pin pbgam bc432 bm680 ort4622 ci ci
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ? 1999 lucent technologies inc. all rights reserved november 1999 ds99-334fpga for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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